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MC68HC05JJ6 MC68HC05JP6
General Release Specification
M68HC05 Microcontrollers
HC05JJ6GRS/D Rev. 3.2 01/2007
freescale.com
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 19 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 39 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Section 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . 69 Section 7. Parallel Input/Output . . . . . . . . . . . . . . . . . . . 77 Section 8. Analog Subsystem . . . . . . . . . . . . . . . . . . . . 103 Section 9. Simple Serial Interface . . . . . . . . . . . . . . . . 137 Section 10. Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . 147 Section 11. Programmable Timer. . . . . . . . . . . . . . . . . 155 Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 171 Section 13. Electrical Specifications . . . . . . . . . . . . . . 189 Section 14. Mechanical Specifications . . . . . . . . . . . . 207 Section 15. Ordering Information . . . . . . . . . . . . . . . . . 211
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General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Table of Contents
Section 1. General Description
1.1 1.2 1.3 1.4 1.5 1.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 VDD and VSS Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.7 OSC1 and OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.7.2 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . .27 1.7.3 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.7.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.7.5 Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . .28 1.8 1.9 1.10 1.11 1.12 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PA0-PA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PB0-PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PC0-PC7 (MC68HC05JP6) . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Section 2. Memory
2.1 2.2 2.3 2.4 2.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Interrupt Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
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2.6 2.7 2.8 2.9 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Section 3. Central Processor Unit (CPU)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .44
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3.2 3.3 3.4 3.5 3.6 3.7 3.8
Section 4. Interrupts
4.1 4.2 4.3 4.4 4.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
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4.6 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6.1 4.6.2 PA0-PA3 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.6.3 IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . .53 4.7 Core Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.7.1 Core Timer Overflow Interrupt. . . . . . . . . . . . . . . . . . . . . . .55 4.7.2 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
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4.8 Programmable Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.1 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.2 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.3 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.9 Serial Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.10 Analog Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.10.1 Comparator Input Match Interrupt . . . . . . . . . . . . . . . . . . . .58 4.10.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Section 5. Resets
5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.5.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . .62 5.5.3 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.5.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.1 CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.2 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.3 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.4 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.5 16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . .66 5.6.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 5.6.7 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.6.8 External Oscillator and Internal Low-Power Oscillator . . . .67
Section 6. Operating Modes
6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Oscillator Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
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6.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6.4.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 6.4.3 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.4.4 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Section 7. Parallel Input/Output
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
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7.2
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . .80 7.3.3 Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.3.4 Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.3.5 Port A Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . .85 7.4.3 Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.4.4 Port B Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.4.5 PB0, PBI, PB2, and PB3 Logic . . . . . . . . . . . . . . . . . . . . . .87 7.4.6 PB4/AN4/TCMP/CMP1 Logic . . . . . . . . . . . . . . . . . . . . . . .89 7.4.7 PB5/SDO Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.4.8 PB6/SDI Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.4.9 PB7/SCK Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.5 Port C (MC68HC05JP6 Only). . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .100 7.5.3 Port C Pulldown Devices. . . . . . . . . . . . . . . . . . . . . . . . . .100 7.5.4 Port C Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.6 Port Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
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Section 8. Analog Subsystem
8.1 8.2 8.3 8.4 8.5 8.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Analog Multiplex Register . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Analog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Analog Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 A/D Conversion Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15
Voltage Comparator Features . . . . . . . . . . . . . . . . . . . . . . . .133 Current Source Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Internal Temperature Sensing Diode Features. . . . . . . . . . . .134 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Port B Interaction with Analog Inputs . . . . . . . . . . . . . . . . . . .135 Port B Pins as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Port B Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 Noise Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Section 9. Simple Serial Interface
9.1 9.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . .140 9.3.3 Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . .140
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8.7 Voltage Measurement Methods . . . . . . . . . . . . . . . . . . . . . . .128 8.7.1 Absolute Voltage Readings . . . . . . . . . . . . . . . . . . . . . . . .129 8.7.1.1 Internal Absolute Reference. . . . . . . . . . . . . . . . . . . . . .129 8.7.1.2 External Absolute Reference . . . . . . . . . . . . . . . . . . . . .130 8.7.2 Ratiometric Voltage Readings. . . . . . . . . . . . . . . . . . . . . .131 8.7.2.1 Internal Ratiometric Reference . . . . . . . . . . . . . . . . . . .131 8.7.2.2 External Ratiometric Reference . . . . . . . . . . . . . . . . . . .131
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9.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Section 10. Core Timer
10.1 10.2 10.3 10.4 10.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Core Timer Status and Control Register . . . . . . . . . . . . . . . .149 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . .151 COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
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Section 11. Programmable Timer
11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Alternate Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .160 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . .164 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Timer Operation during Wait Mode. . . . . . . . . . . . . . . . . . . . .169
NON-DISCLOSURE
11.10 Timer Operation during Stop Mode . . . . . . . . . . . . . . . . . . . .169 11.11 Timer Operation during Halt Mode . . . . . . . . . . . . . . . . . . . . .169
Section 12. Instruction Set
12.1 12.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
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12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .176 12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .177 12.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .178 12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .180 12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 12.5 12.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
Section 13. Electrical Specifications
13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .191 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc). . . . . .192 Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc). . . . . .193 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . .194 DC Electrical Characteristics (3.0 Vdc). . . . . . . . . . . . . . . . . .195
13.10 Analog Subsystem Characteristics (5.0 Vdc) . . . . . . . . . . . . .198 13.11 Analog Subsystem Characteristics (3.0 Vdc) . . . . . . . . . . . . .199 13.12 Control Timing (5.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 13.13 Control Timing (3.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 13.14 SIOP Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . .202
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Table of Contents General Release Specification 11
NON-DISCLOSURE
AGREEMENT
REQUIRED
Table of Contents REQUIRED
13.15 SIOP Timing (VDD = 3.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . .203 13.16 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Section 14. Mechanical Specifications
14.1 14.2 14.3 14.4 14.5 14.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 20-Pin Plastic Dual In-Line Package (Case 738) . . . . . . . . . .208 20-Pin Small Outline Integrated Circuit (Case 751D) . . . . . . .208 28-Pin Plastic Dual In-Line Package (Case 710) . . . . . . . . . .209 28-Pin Small Outline Integrated Circuit (Case 751F) . . . . . . .209
AGREEMENT
Section 15. Ordering Information
15.1 15.2 15.3 15.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 MC68HC05JJ6 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .212 MC68HC05JP6 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .212
NON-DISCLOSURE
General Release Specification 12 Table of Contents
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
List of Figures
Figure 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 5-1 5-2 6-1 6-2 Title Page
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 I/O Registers $0000-$000F . . . . . . . . . . . . . . . . . . . . . . . . .34 I/O Registers $0010-$001F . . . . . . . . . . . . . . . . . . . . . . . . .35 Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 ROM Security Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 68HC05 Programming Model . . . . . . . . . . . . . . . . . . . . . . . .40 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .42 Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . .53 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . .70 Stop/Wait/Halt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .72
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor List of Figures
General Release Specification 13
NON-DISCLOSURE
AGREEMENT
User Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .23 User Mode Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 EPO Oscillator Connections. . . . . . . . . . . . . . . . . . . . . . . . .26
REQUIRED
List of Figures REQUIRED
Figure 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 9-1 9-2 9-3 9-4 9-5 9-6 Title Page
AGREEMENT
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .79 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .80 Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . .81 Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .84 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .85 Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . .86 PB0:PB3 Pin I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 PB4/AN4/TCMP/CMP1 Pin I/O Circuit . . . . . . . . . . . . . . . . .89 PB5/SDO Pin I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . .92 PB6/SDI Pin I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 PB7/SCK Pin I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . .99 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . .100 Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Analog Subsystem Block Diagram . . . . . . . . . . . . . . . . . . .104 Analog Multiplex Register (AMUX) . . . . . . . . . . . . . . . . . . .106 Comparator 2 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . .107 INV Bit Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Analog Control Register (ACR) . . . . . . . . . . . . . . . . . . . . .111 Analog Status Register (ASR) . . . . . . . . . . . . . . . . . . . . . .115 Single-Slope A/D Conversion Method . . . . . . . . . . . . . . . .118 A/D Conversion -- Full Manual Control (Mode 0) . . . . . . .124 A/D Conversion -- Manual/Auto Discharge Control (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 A/D Conversion -- TOF/ICF Control (Mode 2). . . . . . . . . .126 A/D Conversion -- OCF/ICF Control (Mode 3) . . . . . . . . .127 SIOP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 SIOP Timing Diagram (CPHA = 0) . . . . . . . . . . . . . . . . . . .139 SIOP Timing Diagram (CPHA = 1) . . . . . . . . . . . . . . . . . . .140 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . .141 SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . .144 SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . .145
NON-DISCLOSURE
General Release Specification 14 List of Figures
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
List of Figures
Figure 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 13-1
Title
Page
Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .148 Core Timer Status and Control Register (CTSCR) . . . . . .149 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . .151 COP and Security Register (COPR) . . . . . . . . . . . . . . . . .152 Programmable Timer Overall Block Diagram . . . . . . . . . . .157 Programmable Timer Block Diagram . . . . . . . . . . . . . . . . .158 Programmable Timer Registers (TMRH and TMRL) . . . . .159 Alternate Counter Block Diagram. . . . . . . . . . . . . . . . . . . .160 Alternate Counter Registers (ACRH and ACRL) . . . . . . . .161 Timer Input Capture Block Diagram . . . . . . . . . . . . . . . . . .162 Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . .163 Timer Output Compare Block Diagram . . . . . . . . . . . . . . .164 Output Compare Registers (OCRH and OCRL). . . . . . . . .165 Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . .166 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . .168 Overall Internal Operating Frequency Range versus Resistance for VDD = 5 V 10%, -40 C to 85 C . . . . . . . . . . . . . .196 Typical Internal Operating Frequency Range versus Resistance for High VDD Operating Range, 25 C. . . . . . . . . . . . . .196 Overall Internal Operating Frequency Range versus Resistance for VDD = 3 V 10%, -40 C to 85 C . . . . . . . . . . . . . .197 Typical Internal Operating Frequency Range versus Resistance for Low VDD Operating Range, 25 C. . . . . . . . . . . . . .197 SIOP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . .204 Internal Reset Timing Diagram. . . . . . . . . . . . . . . . . . . . . .205 Low-Voltage Reset Timing Diagram. . . . . . . . . . . . . . . . . .205
13-3
13-4
13-5 13-6 13-7 13-8
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor List of Figures
General Release Specification 15
NON-DISCLOSURE
13-2
AGREEMENT
REQUIRED
List of Figures REQUIRED NON-DISCLOSURE
General Release Specification 16 List of Figures
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
List of Tables
Table 4-1 4-2 6-1 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 9-1 Title Page
Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Port B Pin Functions - PB0:PB4 . . . . . . . . . . . . . . . . . . . . . . .91 Port B Pin Functions - PB5:PB7 . . . . . . . . . . . . . . . . . . . . . . .98 Port C Pin Functions (MC68HC05JP6) . . . . . . . . . . . . . . . . .102 Comparator 2 Input Sources. . . . . . . . . . . . . . . . . . . . . . . . . .107 Channel Select Bus Combinations . . . . . . . . . . . . . . . . . . . . .110 A/D Conversion Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 A/D Conversion Parameters . . . . . . . . . . . . . . . . . . . . . . . . . .122 Sample Conversion Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . .123 Absolute Voltage Reading Errors . . . . . . . . . . . . . . . . . . . . . .130 Ratiometric Voltage Reading Errors . . . . . . . . . . . . . . . . . . . .132 Voltage Comparator Setup Conditions . . . . . . . . . . . . . . . . . .133 SIOP Clock Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . .143
10-1 Core Timer Interrupt Rates and COP Timeout Selection . . . .151 10-2 COP Watchdog Recommendations . . . . . . . . . . . . . . . . . . . .153 11-1 Output Compare Initialization Example . . . . . . . . . . . . . . . . .166 12-1 12-2 12-3 12-4 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . .176 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .177 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .179 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .180
General Release Specification List of Tables 17
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
NON-DISCLOSURE
AGREEMENT
Reset/Interrupt Vector Addresses. . . . . . . . . . . . . . . . . . . . . . .47 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
REQUIRED
List of Tables REQUIRED
Table Title Page
12-5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 12-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
NON-DISCLOSURE
General Release Specification 18 List of Tables
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 1. General Description
1.1 Contents
1.2 1.3 1.4 1.5 1.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 VDD and VSS Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.7 OSC1 and OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.7.2 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . .27 1.7.3 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.7.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.7.5 Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . .28 1.8 1.9 1.10 1.11 1.12 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PA0-PA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PB0-PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PC0-PC7 (MC68HC05JP6) . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor General Description
General Release Specification 19
NON-DISCLOSURE
AGREEMENT
REQUIRED
General Description REQUIRED 1.2 Introduction
The Freescale MC68HC05JJ6 and MC68HC05JP6 are ROM versions of the M68HC705JJ and M68HC705JP Families of microcontrollers.
1.3 Features
* * * * * * * Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC05JJ6) or 28-Pin Package (MC68HC05JP6) 6160 Bytes of User ROM, Including 8 Bytes of Security Code and 16 Bytes of User Vectors 224 Bytes of Low-Power User RAM (4 Transistor RAM) 16-Bit Programmable Timer with Input Capture and Output Compare 15-Stage Core Timer, Including 8-Bit Free-Running Counter and 4-Stage, Selectable Real-Time Interrupt Generator Simple Serial Input/Output Port (SIOP) with Interrupt Capability Two Voltage Comparators which Can be Combined with the 16Bit Programmable Timer to Create a 4-Channel, Single-Slope Analog-to-Digital (A/D) Converter Voltage Comparator 1 Output Can Drive the PB4 Port Pin Directly under Software Control 14 Input/Output (I/O) Lines (MC68HC05JJ6) or 22 I/O Lines (MC68HC05JP6), Including High-Source/Sink Current Capability on Six I/O Pins (MC68HC05JJ6) or 14 I/O Pins (MC68HC05JP6) Mask Option Selectable Software Programmable Pulldowns on All I/O Pins and Keyboard Scan Interrupt on Four I/O Pins Software Mask and Request Bit for IRQ Interrupt with Mask Option Selectable Sensitivity on IRQ Interrupt (Edge- and Level-Sensitive or Edge-Only)
NON-DISCLOSURE
AGREEMENT
* *
* *
General Release Specification 20 General Description
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Description
* * * * *
ROM Security Bytes1 to Aid in Locking Out Access to ROM Array Mask Option Selectable Computer Operating Properly (COP) Watchdog System On-Chip Temperature Measurement Diode Mask Option Selectable Low-Voltage Inhibit to Reset CPU in LowVoltage Conditions On-Chip Oscillator with Device Selection of Crystal/Ceramic Resonator or RC Operation and Mask Option Selectable Shunt Resistor, Approximately 2 M Internal Oscillator for Lower-Power Operation, Approximately 100 kHz (500 kHz Selected as a Mask Option) Power-Saving Stop Mode and Wait Mode Instructions (Mask Option Selectable STOP Conversion to Halt and Separate Mask Option for Fast 16-Cycle Restart) Illegal Address Reset Internal Steering Diode and Pullup Device on RESET Pin to VDD
* *
* *
1.4 Mask Options
These MC68HC05JJ6/MC68HC05JP6 mask options are available: * * Sensitivity on External Interrupt, Edge-Triggered or Edge- and Level-Triggered Analog Options: - Comparator 1 Output, Internal Only or Internal and PB4 Pin - Sample and Hold Offset, None of Nominal 100 mV Oscillator Startup Delay, 16 or 4064 Cycles of Internal Bus Cycles STOP Instruction: Enabled or Disabled (Converted to HALT Instruction)
* *
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the ROM difficult for unauthorized users.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor General Description
General Release Specification 21
NON-DISCLOSURE
AGREEMENT
REQUIRED
General Description REQUIRED
* * * * * * On-Chip Oscillator Type, Crystal/Ceramic Resonator Connections or Resistor-Capacitor (RC) Connections Oscillator Shunt Resistor, None or Nominal 2 M Low-Voltage Reset, Enabled or Disabled COP Watchdog Timer, Enabled or Disabled Port A External Interrupt Capability: Enabled or Disabled Nominal Frequency of Internal Low-Power Oscillator, 100 or 500 kHz Software Pulldown Inhibit, Enabled or Disabled
AGREEMENT
*
NOTE:
A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. Any reference to voltage, current, or frequency specified in the following sections will refer to the nominal values. The exact values and their tolerance or limits are specified in Section 13. Electrical Specifications.
1.5 Functional Pin Description NON-DISCLOSURE
Refer to Figure 1-2 for the pinouts of the MC68HC05JJ6 and MC68HC05JP6 in the user mode. A description of the general function of each pin is discussed here.
General Release Specification 22 General Description
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Description
OSC1 OSC2
TRANSFER CONTROL
EXTERNAL OSCILLATOR INTERNAL OSCILLATOR /2
+ COMP1 - + COMP2 -
VDD
CURRENT SOURCE
VDD
LVR
INT
16-BIT TIMER (1) INPUT CAPTURE (1) OUTPUT COMPARE
TCAP TCMP ICF OCF TOF
COMPARATOR CONTROL & MULTIPLEXER
TEMPERATURE DIODE
VSS PB0/AN0 PORT B DATA DIR REG PB1/AN1 PB2/AN2 PORT B PB3/AN3/TCAP PB4/AN4/TCMP/CMP1* PB5/SDO PB6/SDI PB7/SCK
VSS VSS RESET IRQ CPU CONTROL 68HC05 CPU
WATCHDOG & ILLEGAL ADDR DETECT
ALU
INT
ACCUM CPU REGISTERS INDEX REG 0 0 0 0 0 0 0 0 1 1 STK PTR INT PROGRAM COUNTER COND CODE REG 111H I NZC
PA5* PA4* PORT A PA3* PA2* PA1* PA0* PC7**
STATIC RAM (4T) -- 224 BYTES USER ROM -- 6160 BYTES
PORT C DATA DIR REG
PC6** PC5** PORT C PC4** PC3** PC2** PC1** PC0** PORT C ONLY ON 28-PIN MC68HC05JP6
* 15 mA sink capability, maximum of 40 mA into entire port 5 mA source capability, maximum of 20 mA for entire port ** 15 mA sink capability, maximum of 60 mA into entire port 5 mA source capability, maximum of 30 mA for entire port IRQ interrupt capability
Figure 1-1. User Mode Block Diagram
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor General Description General Release Specification 23
NON-DISCLOSURE
SIMPLE SERIAL INTERFACE (SIOP) PORT A DATA DIR REG
AGREEMENT
15-STAGE CORE TIMER SYSTEM
REQUIRED
General Description REQUIRED
MC68HC05JJ6
PB1/AN1 PB2/AN2 PB3/AN3/TCAP *PB4/AN4/TCMP/CMP1 PB5/SDO PB6/SDI PB7/SCK *PA5 * PA4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PB0/AN0 VDD VSS OSC1 OSC2 RESET IRQ PA0* PA1* PA2*
AGREEMENT
* PA3
MC68HC05JP6
PB1/AN1 PB2/AN2 PB3/AN3/TCAP *PB4/AN4/TCMP/CMP1 PB5/SDO * PC4 *PC5 * PC6 *PC7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB0/AN0 VDD VSS OSC1 OSC2 PC3* PC2* PC1* PC0* RESET IRQ PA0* PA1* PA2*
NON-DISCLOSURE
PB6/SDI PB7/SCK *PA5 * PA4
* PA3
* Denotes 10 mA sink /5 mA source capability Denotes IRQ interrupt capability
Figure 1-2. User Mode Pinouts
General Release Specification 24 General Description
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Description
1.6 VDD and VSS Pins
Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.
1.7 OSC1 and OSC2 Pins
The OSC1 and OSC2 pins are the connections for the external pin oscillator (EPO). The OSC1 and OSC2 pins can accept these sets of components: 1. A crystal as shown in Figure 1-3 (a) 2. A ceramic resonator as shown in Figure 1-3 (a) 3. An external resistor as shown in Figure 1-3 (b) 4. An external clock signal as shown in Figure 1-3 (c) The selection of the crystal/ceramic resonator or RC oscillator configuration is done by product part number selection as described in Section 15. Ordering Information. The frequency, fOSC, of the EPO or external clock source is divided by two to produce the internal operating frequency, fOP. An internal 2 M resistor may be selected between OSC1 and OSC2 by the shunt resistor mask option.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor General Description
General Release Specification 25
NON-DISCLOSURE
AGREEMENT
REQUIRED
General Description REQUIRED
MCU 2 M OSC1 OSC2 OSC1
MCU
MCU
OSC2 R
OSC1
OSC2
UNCONNECTED
EXTERNAL CLOCK (a) Crystal or Ceramic Resonator Connections (b) RC Oscillator Connections (c) External Clock Source Connection
AGREEMENT
Figure 1-3. EPO Oscillator Connections
1.7.1 Crystal Oscillator The circuit in Figure 1-3 (a) shows a typical oscillator circuit for an ATcut, parallel resonant crystal. The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately 2 M can be provided by the shunt resistor mask option between OSC1 and OSC2 for the crystal type oscillator. The crystal configuration is enabled by choosing the crystal selection in the oscillator connections mask option.
NON-DISCLOSURE
NOTE:
In general, a 32-kHz crystal is not recommended for use with the EPO on the MC68HC05JJ6/MC68HC05JP6 unless specifically indicated by the crystal manufacturer.
General Release Specification 26 General Description
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Description
1.7.2 Ceramic Resonator Oscillator In cost-sensitive applications, a ceramic resonator can be used in place of the crystal. The circuit in Figure 1-3 (a) can be used for a ceramic resonator. The resonator manufacturer's recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately 2 M can be provided by the shunt resistor mask option between OSC1 and OSC2 for the ceramic resonator type oscillator. The ceramic resonator configuration is enabled by choosing the crystal selection in the connections oscillator mask option.
1.7.3 RC Oscillator The lowest cost oscillator is the RC oscillator configuration where a resistor is connected between the two oscillator pins as shown in Figure 1-3 (b). The internal startup resistor of approximately 2 M is not recommended between OSC1 and OSC2 for the RC-type oscillator. The RC oscillator configuration is selected by the oscillator connections mask option.
1.7.4 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3 (c). This configuration is possible regardless of whether the crystal/ceramic resonator or RC oscillator configuration is used.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor General Description
General Release Specification 27
NON-DISCLOSURE
AGREEMENT
REQUIRED
General Description REQUIRED
1.7.5 Internal Low-Power Oscillator An internal low-power oscillator (LPO) is provided which has a nominal frequency of 100 kHz. This oscillator can be selected via software in place of the external oscillator which uses external components connected to the OSC1 and OSC2 pins. When operating from this internal LPO, the other oscillator can be powered down by software to further conserve power. All standard parts, whether 20 pin, 28 pin, RC option, or crystal, have the nominal frequency of 100 kHz for the LPO. However, a 500-kHz frequency LPO is available also. Either the 100-kHz or the 500-kHz LPO is selected by the low-power oscillator mask option.
AGREEMENT
1.8 RESET Pin
The RESET pin can be used as an input to reset the MCU to a known startup state by pulling it to the low state. It also functions as an output to indicate that an internal COP watchdog, illegal address, or low-voltage reset has occurred. The RESET pin contains a pullup device to allow the pin to be left disconnected without an external pullup resistor. The RESET pin also contains a steering diode that, when the power is removed, will discharge to VDD any charge left on an external capacitor connected between the RESET pin and VSS. The RESET pin also contains an internal Schmitt trigger to improve its noise immunity as an input.
NON-DISCLOSURE
1.9 IRQ Pin
The IRQ input pin drives the asynchronous IRQ interrupt function of the CPU. Using a mask option, the IRQ interrupt function uses either negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If level-sensitive triggering is selected, the IRQ pin requires an external resistor to VDD for "wired-OR" operation. If the IRQ pin is not used, it must be tied to the VDD supply. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin may affect the mode of operation if the
General Release Specification 28 General Description
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Description
voltage on the IRQ pin is above VDD when the device is released from a reset condition.
NOTE:
1.10 PA0-PA5
These six I/O lines comprise port A, a general-purpose bidirectional I/O port. This port also has four pins which have keyboard interrupt capability. All six of these pins have high current source and sink capability. All of these pins have software programmable pulldowns which can be disabled by the software pulldown inhibit mask option.
1.11 PB0-PB7
These eight I/O lines comprise port B, a general-purpose bidirectional I/O port. This port is also shared with the 16-bit programmable timer input capture and output compare functions, with the two voltage comparators in the analog subsystem and with the simple serial interface (SIOP). The outputs of voltage comparator 1 can directly drive the PB4 pin when enabled by mask option; and the PB4 pin has high current source and sink capability. All of these pins have software programmable pulldowns which can be disabled by the software pulldown inhibit mask option.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor General Description
General Release Specification 29
NON-DISCLOSURE
AGREEMENT
Each of the PA0 through PA3 I/O pins may be connected by the port A interrupt mask option as an OR function with the IRQ interrupt function. This capability allows keyboard scan applications where the transitions or levels on the I/O pins will behave the same as the IRQ pin, except that active transitions and levels are inverted. The edge or level sensitivity selected by the mask option for the IRQ pin also applies to the I/O pins that are ORed to create the IRQ signal. For more information, refer to 4.6 External Interrupts.
REQUIRED
General Description REQUIRED 1.12 PC0-PC7 (MC68HC05JP6)
These eight I/O lines comprise port C, a general-purpose bidirectional I/O port. This port is only available on the 28-pin MC68HC05JP6. All eight of these pins have high current source and sink capability. All of these pins have software programmable pulldowns which can be disabled by the software pulldown inhibit mask option.
NON-DISCLOSURE
General Release Specification 30 General Description
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 2. Memory
2.1 Contents
2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Interrupt Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.2 Introduction
This section describes the organization of the memory on the MC68HC05JJ6/MC68HC05JP6.
2.3 Memory Map
The CPU can address eight Kbytes of memory space as shown in Figure 2-1. The ROM portion of memory holds the program instructions, fixed data, user-defined vectors, and interrupt service routines. The RAM portion of memory holds variable data. I/O registers are memory mapped so that the CPU can access their locations in the same way that it accesses all other memory locations.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Memory
General Release Specification 31
NON-DISCLOSURE
AGREEMENT
REQUIRED
Memory REQUIRED
$0000 $001F $0020
I/O REGISTERS 32 BYTES
USER RAM 224 BYTES $00FF $0100 $06FF $0700 STACK RAM 64 BYTES UNIMPLEMENTED 1536 BYTES $00C0 $00FF
AGREEMENT
USER ROM 6136 BYTES $1EF7 $1EF8 $1EFF $1F00 $1FEF $1FF0 $1FFF SECURITY CHECK ROM 8 BYTES INTERNAL TEST ROM 240 BYTES USER VECTORS (ROM) 16 BYTES
Figure 2-1. Memory Map
2.4 Input/Output Registers NON-DISCLOSURE
The first 32 addresses of the memory space, $0000-$001F, contain the I/O Registers section as summarized in Figure 2-2. One I/O register is located outside the 32-byte I/O section, which is the computer operating properly (COP) register mapped at $1FF0. The assignment of each control, status, and data bit in the I/O register space from $0000-$001F is given in Figure 2-3 and Figure 2-4.
General Release Specification 32 Memory
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Memory
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
Register Name Port A Data Register Port B Data Register Port C Data Register * Analog MUX Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register * Unused Core Timer Counter Serial Control Register Serial Status Register Serial Data Register IRQ Status & Control Register Unused Unused Port A and Port C Pulldown Register * Port B Pulldown Register Timer Control Register Timer Status Register Input Capture Register (MSB) Input Capture Register (LSB) Output Compare Register (MSB) Output Compare Register (LSB) Timer Counter Register (MSB) Timer Counter Register (LSB) Alternate Counter Register (MSB) Alternate Counter Register (LSB) Unused Analog Control Register Analog Status Register Reserved Core Timer Status & Control Register
Figure 2-2. I/O Registers
* Features related to port C are available only on the 28-pin MC68HC05JP6 devices.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Memory
General Release Specification 33
NON-DISCLOSURE
AGREEMENT
REQUIRED
Memory REQUIRED
Addr. $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A
Register Port A Data, PORTA Port B Data, PORTB * Port C Data, PORTC Analog MUX Register, AMUX Port A Data Direction, DDRA Port B Data Direction, DDRB * Port C Data Direction, DDRC Unimplemented Core Timer Status/Control, CTSCR Core Timer Counter, CTCR Serial Control, SCR Serial Status, SSR Serial Data, SDR IRQ Status & Control, ISCR Unimplemented Unimplemented
NON-DISCLOSURE
$000B $000C $000D $000E $000F
Read: Write: Read: PB7 Write: Read: PC7 Write: Read: HOLD Write: Read: 0 Write: Read: DDRB7 Write: Read: DDRC7 Write: Read: Write: Read: CTOF Write: Read: BIT 7 Write: Read: SPIE Write: Read: SPIF Write: Read: BIT 7 Write: Read: IRQE Write: Read: Write: Read: Write:
Bit 7 0
6 0
5 PA5 PB5 PC5 INV DDRA5 DDRB5 DDRC5
4 PA4 PB4 PC4 VREF DDRA4 DDRB4 DDRC4
3 PA3 PB3 PC3 MUX4 DDRA3 DDRB3 DDRC3
2 PA2 PB2 PC2 MUX3 DDRA2 DDRB2 DDRC2
1 PA1 PB1 PC1 MUX2 DDRA1 DDRB1 DDRC1
Bit 0 PA0 PB0 PC0 MUX1 DDRA0 DDRB0 DDRC0
PB6 PC6 DHOLD 0
AGREEMENT
DDRB6 DDRC6
RTIF 6
CTOFE 5
RTIE 4
0 CTOFR 3 0 SPIR 0
0 RTIFR 2
RT1 1
RT0 BIT 0
SPE DCOL
LSBF 0
MSTR 0
CPHA 0
SPR1 0
SPR0 0
6 OM2
5 OM1
4 0 R
3 IRQF
2 0
1 0 IRQR
BIT 0 0
= Unimplemented
R
= Reserved
Figure 2-3. I/O Registers $0000-$000F
* Features related to Port C are available only on the 28-pin MC68HC05JP6 devices.
General Release Specification 34 Memory
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Memory
Addr. $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
Register * Port A & Port C Pulldown, PDRA Port B Pulldown, PDRB Timer Control, TCR Timer Status, TSR Input Capture MSB, ICRH Input Capture LSB, ICRL Output Compare MSB, OCRH Output Compare LSB, OCRL Timer Counter MSB, TMRH Timer Counter LSB, TMRL Alternate Counter MSB, ACRH Alternate Counter LSB, ACRL Unimplemented Analog Control, ACR Analog Status, ASR Reserved
ATD2 CPF1 R R
ATD1 0 CPFR2 R R
ICEN 0 CPFR1 R R
CPIE COE1 R R R
CP2EN VOFF R R
CP1EN CMP2 R R
ISEN CMP1 R R R
= Unimplemented
= Reserved
Figure 2-4. I/O Registers $0010-$001F
* Features related to Port C are available only on the 28-pin MC68HC05JP6 devices.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Memory
General Release Specification 35
NON-DISCLOSURE
R/W Bit 7 Read: Write: PDICH Read: Write: PDIB7 Read: ICIE Write: Read: ICF Write: Read: BIT15 Write: Read: BIT7 Write: Read: BIT15 Write: Read: BIT 7 Write: Read: BIT15 Write: Read: BIT 7 Write: Read: BIT15 Write: Read: BIT 7 Write: Read: Write: Read: CHG Write: Read: CPF2 Write: Read: R Write: R
6 PDICL PDIB6 OCIE OCF 14 6
5 PDIA5 PDIB5 TOIE TOF 13 5
4 PDIA4 PDIB4 0 0 12 4
3 PDIA3 PDIB3 0 0 11 3
2 PDIA2 PDIB2 0 0 10 2
1 PDIA1 PDIB1 IEDG 0 9 1
Bit 0 PDIA0 PDIB0 OLVL 0 BIT8 BIT0
14 6 14 6 14 6
13 5 13 5 13 5
12 4 12 4 12 4
11 3 11 3 11 3
10 2 10 2 10 2
9 1 9 1 9 1
BIT 8 BIT 0 BIT 8 BIT 0 BIT 8 BIT 0
AGREEMENT
REQUIRED
Memory REQUIRED 2.5 Interrupt Vector Mapping
The interrupt vectors are contained in the upper memory addresses above $1FF0 as shown in Figure 2-5.
Address $1FF0 $1FF1 $1FF2 $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF Register Name COP Register Unused Analog Interrupt Vector (MSB) Analog Interrupt Vector (LSB) Serial Interrupt Vector (MSB) Serial Interrupt Vector ((LSB) Timer Interrupt Vector (MSB) Timer Interrupt Vector (LSB) CTimer Interrupt Vector (MSB) CTimer Interrupt Vector (LSB) External IRQ Vector (MSB) External IRQ Vector (LSB) SWI Vector (MSB) SWI Vector (LSB) Reset Vector (MSB) Reset Vector (LSB)
NON-DISCLOSURE
AGREEMENT
Figure 2-5. Vector Mapping
2.6 RAM
The 224 addresses from $0020 to $00FF serve as both the user RAM and the stack RAM. The CPU uses five RAM bytes to save all CPU register contents before processing an interrupt. During a subroutine call, the CPU uses two bytes to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
General Release Specification 36 Memory
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Memory
2.7 ROM
The ROM is located in three areas of the memory map: * * * Addresses $0700-$1EF7 contain 6136 bytes of user ROM. Addresses $1EF8-$1EFF contain eight bytes for security code. Addresses $1FF0-1FFF contain 16 bytes of ROM reserved for user vectors and COP register.
2.8 ROM Security
The MC68HC05JJ6/MC68HC05JP6 contains a ROM security feature1 that requires that the proper data sequence be presented to port B before the internal ROM contents can be read in any of the expanded bus modes used for testing. The bytes to match are placed at ROM locations $1EF8 through $1EFF as shown in Figure 2-6.
Address $1EF8 $1EF9 $1EFA $1EFB $1EFC $1EFD $1EFE $1EFF Register Name 1st ROM Security Check Byte 2nd ROM Security Check Byte 3rd ROM Security Check Byte 4th ROM Security Check Byte 5th ROM Security Check Byte 6th ROM Security Check Byte 7th ROM Security Check Byte 8th ROM Security Check Byte
Figure 2-6. ROM Security Bytes
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the ROM difficult for unauthorized users.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Memory
General Release Specification 37
NON-DISCLOSURE
AGREEMENT
REQUIRED
Memory REQUIRED 2.9 COP Register
As shown in Figure 2-7, a register location is provided at $1FF0 to reset the COP watchdog timer.
$1FF0
Bit 7
6
5
4
3
2
1
Bit 0
Read: Write: COPC Unaffected by Reset = Unimplemented
AGREEMENT
Reset:
Figure 2-7. COP Register (COPR)
NON-DISCLOSURE
General Release Specification 38 Memory
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2 3.3 3.4 3.5 3.6 3.7 3.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .44
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Central Processor Unit (CPU)
General Release Specification 39
NON-DISCLOSURE
AGREEMENT
REQUIRED
Central Processor Unit (CPU) REQUIRED 3.2 Introduction
This section describes the CPU registers. Figure 3-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 A 7 X 0 INDEX REGISTER (X) 0 SP 0 PCL 7 1 1 5 1 4 H I N Z 0 C CONDITION CODE REGISTER (CCR) PROGRAM COUNTER (PC) STACK POINTER (SP) 0 ACCUMULATOR (A)
AGREEMENT
15 0 15 1 1 1 0 0 0 0 0 10 PCH 0 0 8 1 7
6 1
5
HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG
NON-DISCLOSURE
Figure 3-1. 68HC05 Programming Model
3.3 Accumulator
The accumulator is a general-purpose 8-bit register as shown in Figure 3-2. The CPU uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations.
Bit 7 Read: Write: Reset: Unaffected by Reset 6 5 4 3 2 1 Bit 0
Figure 3-2. Accumulator (A)
General Release Specification 40
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
3.4 Index Register
The index register is a general-purpose 8-bit register as shown in Figure 3-3. In the indexed addressing modes, the CPU uses the byte in the index register to determine the conditional address of the operand.
Bit 7 Read: Write: Reset: Unaffected by Reset 6 5 4 3 2 1 Bit 0
Figure 3-3. Index Register (X) The 8-bit index register can also serve as a temporary data storage location.
3.5 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack as shown in Figure 3-4. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer initializes to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Bit 15 Read: 0 Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 3-4. Stack Pointer (SP) The 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations; an interrupt uses five locations.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Central Processor Unit (CPU)
General Release Specification 41
NON-DISCLOSURE
AGREEMENT
REQUIRED
Central Processor Unit (CPU) REQUIRED 3.6 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched as shown in Figure 3-5. The three most significant bits of the program counter are ignored internally and appear as 111 during stacking and subroutine calls. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
Bit 15 Read: 1 Write: Reset: 0 0 0 Loaded with Vector from $1FFE and $1FFF 1 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
AGREEMENT
Figure 3-5. Program Counter (PC)
3.7 Condition Code Register NON-DISCLOSURE
The condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111 as shown in Figure 3-6. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: 1 Write: Reset: 1 U = Unaffected 1 1 U 1 U U U 1 1 H I N C Z 6 5 4 3 2 1 Bit 0
Figure 3-6. Condition Code Register (CCR)
General Release Specification 42
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
Half-Carry Flag (H) The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half-carry flag is required for binary coded decimal (BCD) arithmetic operations. Reset has no effect on the half-carry flag. Interrupt Mask (I) Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is a logic zero, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. The CPU processes the latched interrupt as soon as the interrupt mask is cleared again. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state. After a reset, the interrupt mask is set and can be cleared only by a CLI instruction. Negative Flag (N) The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. Reset has no effect on the negative flag. Zero Flag (Z) The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. Reset has no effect on the zero flag. Carry/Borrow Flag (C) The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. Reset has no effect on the carry/borrow flag.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Central Processor Unit (CPU)
General Release Specification 43
NON-DISCLOSURE
AGREEMENT
REQUIRED
Central Processor Unit (CPU) REQUIRED 3.8 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations.
NON-DISCLOSURE
General Release Specification 44
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Central Processor Unit (CPU) Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 4. Interrupts
4.1 Contents
4.2 4.3 4.4 4.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.6 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6.1 4.6.2 PA0-PA3 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.6.3 IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . .53 4.7 Core Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.7.1 Core Timer Overflow Interrupt. . . . . . . . . . . . . . . . . . . . . . .55 4.7.2 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.8 Programmable Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.1 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.2 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.3 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.9 Serial Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.10 Analog Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.10.1 Comparator Input Match Interrupt . . . . . . . . . . . . . . . . . . . .58 4.10.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Interrupts
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An interrupt temporarily stops normal program execution to process a particular event. An interrupt does not stop the execution of the instruction in progress, but takes effect when the current instruction completes its execution. Interrupt processing automatically saves the CPU registers on the stack and loads the program counter with a user-defined vector address.
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4.3 Interrupt Vectors
Table 4-1 summarizes the reset and interrupt sources and vector assignments.
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General Release Specification 46 Interrupts
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Interrupts
Table 4-1. Reset/Interrupt Vector Addresses
Function Source Power-On Logic RESET Pin Low-Voltage Reset Illegal Address Reset COP Watchdog Software Interrupt (SWI) User Code IRQ Pin External Interrupt (IRQ) PA3 Pin PA2 Pin PA1 Pin PA0 Pin TOF Bit RTIF Bit ICF Bit OCF Bit TOF Bit SPIF Bit CPF1 Bit CPF2 Bit Mask Options Global Hardware Mask Local Software Mask Priority (1 = Highest) Vector Address
Reset
--
--
--
1
$1FFE-$1FFF
Enable -- -- I Bit IRQE Bit 2 $1FFA-$1FFB -- -- Same Priority As Instruction $1FFC-$1FFD
Enable
Core Timer Interrupts Programmable Timer Interrupts Serial Interrupt Analog Interrupt
--
I Bit
TOFE Bit RTIE Bit ICIE Bit OCIE Bit TOIE Bit SPIE Bit CPIE Bit
3
$1FF8-$1FF9
--
I Bit
4
$1FF6-$1FF7
-- --
I Bit I Bit
5 6
$1FF4-$1FF5 $1FF2-$1FF3
NOTE:
If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt first. A higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the I bit.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Interrupts
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The CPU does these actions to begin servicing an interrupt: * * * Stores the CPU registers on the stack in the order shown in Figure 4-1 Sets the I bit in the condition code register to prevent further interrupts Loads the program counter with the contents of the appropriate interrupt vector locations as shown in Table 4-1
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The return-from-interrupt (RTI) instruction causes the CPU to recover its register contents from the stack as shown in Figure 4-1. The sequence of events caused by an interrupt is shown in the flowchart in Figure 4-2.
$0020 $0021
Bottom of RAM
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$00BE $00BF $00C0 $00C1 $00C2
Bottom of Stack Unstacking Order 1 2 3 4 5
n n+1 n+2 n+3 n+4
Condition Code Register Accumulator Index Register Program Counter (High Byte) Program Counter (Low Byte)
$00FD $00FE $00FF
5 4 3 2 1 Stacking Order
Top of Stack (RAM)
Figure 4-1. Interrupt Stacking Order
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FROM RESET
YES
I BIT SET? NO
EXTERNAL INTERRUPT? NO
YES
CLEAR IRQ LATCH
CORE TIMER INTERRUPT? NO TIMER INTERRUPT? NO SERIAL INTERRUPT? NO ANALOG INTERRUPT? NO
YES
YES
YES
YES STACK PCL, PCH, X, A, CCR SET I BIT LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? NO RTI INSTRUCTION? NO
YES
YES
UNSTACK CCR, A, X, PCH, PCL
EXECUTE INSTRUCTION
Figure 4-2. Interrupt Flowchart
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Interrupts General Release Specification 49
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The software interrupt (SWI) instruction causes a non-maskable interrupt.
4.6 External Interrupts
These sources can generate external interrupts: * * IRQ pin PA3-PA0 pins
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Setting the I bit in the condition code register or clearing the IRQE bit in the interrupt status and control register disables these external interrupts.
4.6.1 IRQ Pin An interrupt signal on the IRQ pin latches an external interrupt request. To help clean up slow edges, the input from the IRQ pin is processed by a Schmitt trigger gate. When the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register (CCR) and the IRQE bit in the IRQ status and control register (ISCR). If the I bit is clear and the IRQE bit is set, then the CPU begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. Figure 4-3 shows the logic for external interrupts.
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NOTE:
If the IRQ pin is not in use, it should be connected to the VDD pin. The IRQ pin can be negative edge-triggered only or negative edge- and low level-triggered. This external interrupt sensitivity is selected with the external interrupt sensitivity mask option.
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MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Interrupts
With the edge- and level-sensitive trigger option, a falling edge or a low level on the IRQ pin latches an external interrupt request. The edge- and level-sensitive trigger mask option allows connection to the IRQ pin of multiple wired-OR interrupt sources. As long as any source is holding the IRQ low, an external interrupt request is present, and the CPU continues to execute the interrupt service routine. With the edge-sensitive-only trigger mask option, a falling edge on the IRQ pin latches an external interrupt request. A subsequent interrupt request can be latched only after the voltage level on the IRQ pin returns to a logic one and then falls again to logic zero.
IRQ
TO BIH & BIL INSTRUCTION PROCESSING
PA3 VDD
PA2
R PA1
EXTERNAL INTERRUPT REQUEST
PA0 KEYBOARD INTERRUPT MASK OPTION (ENABLE = 1) EDGE- OR EDGE- AND LEVEL MASK OPTION (ENABLE=1) INTERNAL DATA BUS
RST IRQ VECTOR FETCH IRQR IRQE IRQF
IRQ STATUS/CONTROL REGISTER ($000D)
Figure 4-3. External Interrupt Logic
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IRQ LATCH
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NOTE:
The response of the IRQ pin can be affected if the external interrupt capability of the PA0 through PA3 pins is enabled by mask option. If the port A pins are enabled as external interrupts, then any high level on a PA0 through PA3 pin will cause the IRQ changes and state to be ignored until all of the PA0 through PA3 pins have returned to a low level.
4.6.2 PA0-PA3 Pins The port A interrupt mask option that enables the PA0 through PA3 pins (PA0:PA3) to serve as additional external interrupt sources is available. When this mask option is enabled, a rising edge on a PA0:PA3 pin latches an external interrupt request. After completing the current instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register and the IRQE bit in the ISCR. If the I bit is clear and the IRQE bit is set, the CPU then begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. The PA0:PA3 pins can be edge-triggered or edge- and level-triggered depending upon the mask option selection for the IRQ pin. With the edge- and level-sensitive trigger mask option, a rising edge or a high level on a PA0:PA3 pin latches an external interrupt request. The edge- and level-sensitive trigger mask option allows connection to a PA0:PA3 pin of multiple wired-OR interrupt sources. As long as any source is holding the pin high, an external interrupt request is present, and the CPU continues to execute the interrupt service routine. With the edge-sensitive only trigger mask option, a rising edge on a PA0:PA3 pin latches an external interrupt request. A subsequent external interrupt request can be latched only after the voltage level of the previous interrupt signal returns to a logic zero and then rises again to a logic one.
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Interrupts
NOTE:
If the port A pins are enabled by mask option as external interrupts, then a high level on any PA0:PA3 pin will drive the state of the IRQ function such that the IRQ pin and other PA0:PA3 pins will be ignored until ALL of the PA0:PA3 pins have returned to a low level. Similarly, if the IRQ pin is at a low level, the PA0:PA3 pins will be ignored until the IRQ pin returns to a high state.
4.6.3 IRQ Status and Control Register The IRQ status and control register (ISCR), shown in Figure 4-4, contains an external interrupt mask (IRQE), an external interrupt flag (IRQF), and a flag reset bit (IRQR). Unused bits will read as logic zeros. The ISCR also contains two control bits for the oscillators, external pin oscillator, and internal low-power oscillator. Reset sets the IRQE and OM2 bits; and clears all the other bits.
$000D Read: IRQE Write: Reset: 1 1 0 OM2 OM1 R 0 0 R 0
= Reserved
Bit 7
6
5
4 0
3 IRQF
2 0
1 0 IRQR U
Bit 0 0
0
= Unimplemented
Figure 4-4. IRQ Status and Control Register (ISCR) IRQE -- External Interrupt Request Enable This read/write bit enables external interrupts. Reset sets the IRQE bit. 1 = External interrupt processing enabled 0 = External interrupt processing disabled OM1 and OM2 -- Oscillator Selects These bits control the selection and enabling of the oscillator source for the MCU. One choice is the internal low-power oscillator (LPO). The other choice is the external pin oscillator (EPO) which is common to most MC68HC05 MCU devices. The EPO uses external
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components like filter capacitors and a crystal or ceramic resonator and consumes more power. The selection and enable conditions for these two oscillators are shown in Table 4-2. Table 4-2. Oscillator Selection
OM2
0
OM1
0 1 0 1
Oscillator Selected by CPU
Internal External Internal Internal
Internal Low-Power Oscillator (LPO)
Enabled Disabled Enabled Enabled
External Pin Oscillator (EPO)
Disabled Enabled Disabled Enabled
Power Consumption
Lowest Normal Lowest Normal
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0 1 1
Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2 set is provided so that the EPO can be started and allowed to stabilize while the LPO still clocks the MCU. The reset state is for OM1 to be cleared and OM2 to be set, which selects the LPO and disables the EPO. IRQF -- External Interrupt Request Flag The IRQ flag is a clearable, read-only bit that is set when an external interrupt request is pending. Writing to the IRQF bit has no effect. Reset clears the IRQF bit. 1 = Interrupt request pending 0 = No interrupt request pending These conditions set the IRQ flag: * * An external interrupt signal on the IRQ pin An external interrupt signal on pins PA0, PA1, PA2, or PA3 when the PA0 through PA3 pins are enabled by a mask option to serve as external interrupt sources
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These conditions clear the IRQ flag: * * When the CPU fetches the interrupt vector When a logic one is written to the IRQR bit
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MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Interrupts
IRQR -- Interrupt Request Reset This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines. Writing a logic one to IRQR clears the IRQF. Writing a logic zero to IRQR has no effect. IRQR always reads as a logic zero. Reset has no effect on IRQR. 1 = Clear IRQF flag bit 0 = No effect
The core timer can generate the two interrupts: * * Timer overflow interrupt Real-time interrupt
Setting the I bit in the condition code register disables core timer interrupts. The controls and flags for these interrupts are in the Core Timer status and control register (CTSCR) located at $0008.
4.7.1 Core Timer Overflow Interrupt An overflow interrupt request occurs if the core timer overflow flag (TOF) becomes set while the core timer overflow interrupt enable bit (TOFE) is also set. The TOF flag bit can be reset by writing a logical one to the CTOFR bit in the CTSCR or by a reset of the device.
4.7.2 Real-Time Interrupt A real-time interrupt request occurs if the real-time interrupt flag (RTIF) becomes set while the real-time interrupt enable bit (RTIE) is also set. The RTIF flag bit can be reset by writing a logical one to the RTIFR bit in the CTSCR or by a reset of the device.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Interrupts
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4.7 Core Timer Interrupts
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The 16-bit programmable timer can generate an interrupt whenever these events occur: * * * Input capture Output compare Timer counter overflow
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Setting the I bit in the condition code register disables timer interrupts. The controls for these interrupts are in the timer control register (TCR) located at $0012 and in the status bits in the timer status register (TSR) located at $0013.
4.8.1 Input Capture Interrupt An input capture interrupt occurs if the input capture flag (ICF) becomes set while the input capture interrupt enable bit (ICIE) is also set. The ICF flag bit is in the TSR, and the ICIE enable bit is located in the TCR. The ICF flag bit is cleared by a read of the TSR with the ICF flag bit set and then followed by a read of the LSB of the input capture register (ICRL) or by reset. The ICIE enable bit is unaffected by reset.
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4.8.2 Output Compare Interrupt An output compare interrupt occurs if the output compare flag (OCF) becomes set while the output compare interrupt enable bit (OCIE) is also set. The OCF flag bit is in the TSR and the OCIE enable bit is in the TCR. The OCF flag bit is cleared by a read of the TSR with the OCF flag bit set, and then followed by an access to the LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is unaffected by reset.
General Release Specification 56 Interrupts
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Interrupts
4.8.3 Timer Overflow Interrupt A timer overflow interrupt occurs if the timer overflow flag (TOF) becomes set while the timer overflow interrupt enable bit (TOIE) is also set. The TOF flag bit is in the TSR and the TOIE enable bit is in the TCR. The TOF flag bit is cleared by a read of the TSR with the TOF flag bit set and then followed by an access to the LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected by reset.
The simple serial interface can generate the two interrupts: * * Receive sequence complete Transmit sequence complete
Setting the I bit in the condition code register disables serial interrupts. The controls for these interrupts are in the serial control register (SCR) located at $000A and in the status bits in the serial status register (SSR) located at $000B. A transfer complete interrupt occurs if the serial interrupt flag (SPIF) becomes set while the serial interrupt enable bit (SPIE) is also set. The SPIF flag bit is in the serial status register (SSR) located at $000B, and the SPIE enable bit is located in the serial control register (SCR) located at $000A. The SPIF flag bit is cleared by a read of the SSR with the SPIF flag bit set, and then followed by a read or write to the serial data register (SDR) located at $000C. The SPIF flag bit can also be reset by writing a one to the SPIR bit in the SCR.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Interrupts
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4.9 Serial Interrupts
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The analog subsystem can generate these interrupts: * * * Voltage on positive input of comparator 1 is greater than the voltage on the negative input of comparator 1. Voltage on positive input of comparator 2 is greater than the voltage on the negative input of comparator 2. Trigger of the input capture interrupt from the programmable timer as described in 4.8.1 Input Capture Interrupt
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Setting the I bit in the condition code register disables analog subsystem interrupts. The controls for these interrupts are in the analog subsystem control register (ACR) located at $001D, and the status bits are in the analog subsystem status register (ASR) located at $001E.
4.10.1 Comparator Input Match Interrupt A comparator input match interrupt occurs if either compare flag bit (CPF1 or CPF2) in the ASR becomes set while the comparator interrupt enable bit (CPIE) in the ACR is also set. The CPF1 and CPF2 flag bits can be reset by writing a one to the corresponding CPFR1 or CPFR2 bits in the ASR. Reset clears these bits.
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4.10.2 Input Capture Interrupt The analog subsystem can also generate an input capture interrupt through the 16-bit programmable timer. The input capture can be triggered when there is a match in the input conditions for the voltage comparator 2. If comparator 2 sets the CP2F flag bit in the ASR and the input capture enable (ICEN) in the ACR is set, then an input capture will be performed by the programmable timer. If the ICIE enable bit in the TCR is also set, then an input compare interrupt will occur. Reset clears these bits.
NOTE:
For the analog subsystem to generate an interrupt using the input capture function of the programmable timer, the ICEN enable bit in the ACR and the ICIE and IEDG bits in the TCR must all be set.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Interrupts Freescale Semiconductor
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General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 5. Resets
5.1 Contents
5.2 5.3 5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.5.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . .62 5.5.3 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.5.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.1 CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.2 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.3 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.4 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.5 16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . .66 5.6.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 5.6.7 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.6.8 External Oscillator and Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .67
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This section describes the five reset sources and how they initialize the MCU. A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address. These conditions produce a reset: * * * * * Initial power-up of device (power-on reset) A logic zero applied to the RESET pin (external reset) Timeout of the COP watchdog (COP reset) Low voltage applied to the device (LVR reset) Fetch of an opcode from an address not in the memory map (illegal address reset)
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Figure 5-1 shows a block diagram of the reset sources and their interaction.
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LVR MASK OPTION (ENABLE = 1)
COP MASK OPTION (ENABLE = 1)
COP WATCHDOG LOW-VOLTAGE RESET VDD POWER-ON RESET ILLEGAL ADDRESS RESET INTERNAL ADDRESS BUS RESET S D RESET LATCH R 3-CYCLE CLOCKED 1-SHOT INTERNAL CLOCK RST TO CPU AND SUBSYSTEMS
Figure 5-1. Reset Sources
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5.3 Power-On Reset
A positive transition on the VDD pin generates a power-on reset. The power-on reset is strictly for conditions during powering up and cannot be used to detect drops in power supply voltage. A delay of 16 or 4064 internal bus cycles (tCYC) after the oscillator becomes active allows the clock generator to stabilize. If the RESET pin is at logic zero at the end of this multiple tCYC time, the MCU remains in the reset condition until the signal on the RESET pin goes to a logic one.
5.4 External Reset
A logic zero applied to the RESET pin for one and one half tCYC generates an external reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. The external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the internal RST signal that resets the CPU and peripherals. The RESET pin can also be pulled to a low state by an internal pulldown device that is activated by three internal reset sources. This RESET pulldown device will be asserted only for three to four cycles of the internal bus or as long as the internal reset source is asserted.
NOTE:
Do not connect the RESET pin directly to VDD, as this may overload some power supply designs if the internal pulldown on the RESET pin should activate.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Resets
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The four internally generated resets are: * * * * Initial power-on reset function COP watchdog timer reset Low-voltage reset Illegal address detector
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Only the COP watchdog timer reset, low-voltage reset, and illegal address detector will also assert the pulldown device on the RESET pin for the duration of the reset function or for three to four internal bus cycles, whichever is longer.
5.5.1 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). Depending on a mask option, there is an oscillator stabilization delay of 16 or 4064 internal bus cycles after the oscillator becomes active. The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of the 16 or 4064 cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will not activate the pulldown device on the RESET pin. VDD must drop below VPOR for the internal POR circuit to detect the next rise of VDD.
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5.5.2 Computer Operating Properly (COP) Reset A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. To clear the COP watchdog and prevent a COP reset, write a logic zero to the COPC bit of the COP register at location $1FF0. The COP register, shown in
General Release Specification 62 Resets MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Resets
Figure 5-2, is a write-only register that returns the contents of a ROM location when read.
$1FF0 Read: Write: Reset: = Unimplemented Unaffected by Reset COPC Bit 7 6 5 4 3 2 1 Bit 0
Figure 5-2. COP Register (COPR) COPC -- COP Clear COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the COP watchdog from resetting the MCU. Reset clears the COPC bit. 1 = No effect on COP watchdog timer 0 = Reset COP watchdog timer The COP watchdog reset will assert the pulldown device to pull the RESET pin low for three to four cycles of the internal bus. The COP watchdog reset function can be enabled or disabled by the COP watchdog timer mask option.
5.5.3 Low-Voltage Reset (LVR) The LVR activates the RST reset signal to reset the device when the voltage on the VDD pin falls below the LVR trip voltage. The LVR will assert the pulldown device to pull the RESET pin low for three to four cycles of the internal bus. The LVR reset function can be enabled or disabled by the low-voltage reset mask option.
NOTE:
The LVR is guaranteed for applications where the VDD supply voltage normally operates above 4.5 volts. Devices that have the LVR mask option selected cannot be operated at the 3-V operating range.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Resets
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5.5.4 Illegal Address Reset An opcode fetch (execution of an instruction) at an address that is not in the ROM (locations $0700-$1FFF) or the RAM (locations $0020-$00FF) generates an illegal address reset. The illegal address reset will assert the pulldown device to pull the RESET pin low for three to four cycles of the internal bus.
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5.6 Reset States
The following paragraphs describe how the various resets initialize the MCU.
5.6.1 CPU A reset has these effects on the CPU: * * * Loads the stack pointer with $FF Sets the I bit in the condition code register, inhibiting interrupts Loads the program counter with the user-defined reset vector from locations $1FFE and $1FFF Clears the stop latch, enabling the CPU clock Clears the wait latch, bringing the CPU out of the wait mode
NON-DISCLOSURE
* *
General Release Specification 64 Resets
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Resets
5.6.2 I/O Registers A reset has these effects on I/O registers: * Clears bits in data direction registers configuring pins as inputs: - DDRA5-DDRA0 in DDRA for port A - DDRB7-DDRB0 in DDRA for port B - DDRC7-DDRC0 in DDRC for Port C * Clears bits in pulldown inhibit registers to enable pulldown devices: - PDIA5-PDIA0 in PDRA for port A - PDIB7-PDIB0 in PDRB for port B - PDICH and PDICL in PDRA for port C * Has no effect on port A, B, or C* data registers Sets the IRQE bit in the interrupt status and control register (ISCR)
*
* *
5.6.3 Core Timer A reset has these effects on the core timer: * * * Clears the core timer counter register (CTCR) Clears the core timer interrupt flag and enable bits in the core timer status and control register (CTSCR) Sets the real-time interrupt rate selection bits (RT0 and RT1) such that the device will start with the longest real-time interrupt and longest COP timeout delays
5.6.4 COP Watchdog A reset clears the COP watchdog timeout counter.
* Features related to port C are available only on the 28-pin MC68HC705JP6 devices.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Resets
General Release Specification 65
NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets REQUIRED
5.6.5 16-Bit Programmable Timer A reset has these effects on the 16-bit programmable timer: * * * Initializes the timer counter registers (TMRH and TMRL) to a value of $FFFC Initializes the alternate timer counter registers (ACRH and ACRL) to a value of $FFFC Clears all the interrupt enables and the output level bit (OLVL) in the timer control register (TCR) Does not affect the input capture edge bit (IEDG) in the TCR Does not affect the interrupt flags in the timer status register (TSR) Does not affect the input capture registers (ICRH and ICRL) Does not affect the output compare registers (OCRH and OCRL)
AGREEMENT
* * * *
5.6.6 Serial Interface A reset has these effects on the serial interface: * Clears all bits in the SIOP control register (SCR) Clears all bits in the SIOP status register (SSR) Does not affect the contents of the SIOP data register (SDR)
NON-DISCLOSURE
* *
A reset, therefore, disables the SIOP and leaves the shared port B pins as general I/O. Any pending interrupt flag is cleared and the SIOP interrupt is disabled. Also the baud rate defaults to the slowest rate.
General Release Specification 66 Resets
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Resets
5.6.7 Analog Subsystem A reset has these effects on the analog subsystem: * * * Clears all the bits in the multiplex register (AMUX) bits except the hold switch bit (HOLD) which is set Clears all the bits in the analog control register (ACR) Clears all the bits in the analog status register (ASR)
5.6.8 External Oscillator and Internal Low-Power Oscillator A reset presets the oscillator select bits (OM1 and OM2) in the interrupt status and control register (ISCR) such that the device runs from the internal oscillator (OM1 = 0, OM2 = 1) which has these effects on the oscillators: * * * The internal low-power oscillator is enabled and selected. The external oscillator is disabled. The CPU bus clock is driven from the internal low-power oscillator.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Resets
General Release Specification 67
NON-DISCLOSURE
AGREEMENT
A reset, therefore, connects the negative input of comparator 2 to the channel selection bus, which is switched to VSS. Both comparators are set up as non-inverting (a higher positive voltage on the positive input results in a positive output) and both are powered down. The current source and discharge device on the PB0/AN0 pin is disabled and powered down. Any analog subsystem interrupt flags are cleared and the analog interrupt is disabled. Direct drive by comparator 1 to the PB4 pin and the voltage offset to the sample capacitor are disabled (if both are enabled by the analog options mask option).
REQUIRED
Resets REQUIRED NON-DISCLOSURE
General Release Specification 68 Resets
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 6. Operating Modes
6.1 Contents
6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Oscillator Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6.4.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 6.4.3 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.4.4 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.2 Introduction
This section describes the operation of the device with respect to the oscillator source and the low-power modes: * * * * Stop mode Wait mode Halt mode Data-retention mode
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Operating Modes
General Release Specification 69
NON-DISCLOSURE
AGREEMENT
REQUIRED
Operating Modes REQUIRED 6.3 Oscillator Source
The MCU can be clocked by either an internal low-power oscillator (LPO) without external components or by an external pin oscillator (EPO) which uses external components. The enable and selection of the clock source is determined by the state of the oscillator select bits (OM1 and OM2) in the interrupt status and control register (ISCR) as shown in Figure 6-1.
$000D Bit 7 IRQE 1 6 OM2 1 5 OM1 0 4 0 R 0 R 0 = Reserved 0 3 IRQF 2 0 1 0 IRQR U U = Unaffected 0 Bit 0 0
AGREEMENT
Read: Write: Reset:
= Unimplemented
Figure 6-1. IRQ Status and Control Register (ISCR) IRQE -- External Interrupt Request Enable This read/write bit enables external interrupts. Refer to Section 4. Interrupts for more details. OM1 and OM2 -- Oscillator Selects These bits control the selection and enabling of the oscillator source for the MCU. One choice is the internal LPO and the other oscillator is the EPO which is common to most MC68HC05 MCU devices. The EPO uses external components like filter capacitors and a crystal or ceramic resonator and consumes more power than the LPO. The selection and enable conditions for these two oscillators are shown in Table 6-1. Reset clears OM1 and sets OM2, which selects the LPO and disables the EPO.
.
NON-DISCLOSURE
Table 6-1. Oscillator Selection
OM2
0 0 1 1
OM1
0 1 0 1
Oscillator Selected
Internal External Internal Internal
Internal Low-Power Oscillator (LPO)
Enabled Disabled Enabled Enabled
External Pin Power Oscillator Consumption (EPO)
Disabled Enabled Disabled Enabled Lowest Normal Lowest Normal
General Release Specification 70 Operating Modes
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Operating Modes
Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2 set is provided so that the EPO can be started up and allowed to stabilize while the LPO still clocks the MCU.
NOTE:
When switching between oscillators, the user must be careful to ensure that the newly selected oscillator has been enabled and powered up long enough to stabilize before shifting clock sources. Always select the case where both OM1 and OM2 are set and remain at this state for at least 4096 EPO clock cycles if going from the LPO to the EPO or 16 LPO cycles if going from the EPO to the LPO. IRQF -- External Interrupt Request Flag The IRQF flag is a clearable, read-only bit that is set when an external interrupt request is pending. Refer to Section 4. Interrupts for more details. IRQR -- Interrupt Request Reset This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines. Refer to Section 4. Interrupts for more details.
Four modes of operation reduce power consumption: * * * * Stop mode Wait mode Halt mode Data-retention mode
Figure 6-2 shows the sequence of events in stop, wait, and halt modes.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Operating Modes
General Release Specification 71
NON-DISCLOSURE
6.4 Low-Power Modes
AGREEMENT
REQUIRED
Operating Modes REQUIRED
STOP
HALT
WAIT
HALT MASK OPTION? NO
YES
CLEAR I BIT IN CCR SET IRQE BIT IN ISCR TURN OFF CPU CLOCK KEEP OTHER MODULE CLOCKS ACTIVE
CLEAR I BIT IN CCR SET IRQE BIT IN ISCR TURN OFF CPU CLOCK KEEP OTHER MODULE CLOCKS ACTIVE
AGREEMENT
CLEAR I BIT IN CCR SET IRQE BIT IN ISCR CLEAR CTOF, RTIF, CTOFE, AND RTIE BITS IN TSCR CLEAR ICF, OCF, AND TOF BITS IN TSR CLEAR ICIE, OCIE, AND TOIE BITS IN TCR DISABLE EXTERNAL PIN OSCILLATOR TURN OFF INTERNAL LOW-POWER OSCILLATOR
YES
EXTERNAL RESET? NO
YES
EXTERNAL RESET? NO
EXTERNAL RESET? NO
YES
YES
EXTERNAL INTERRUPT? NO
YES
EXTERNAL INTERRUPT? NO
EXTERNAL INTERRUPT? NO
YES
YES
CORE TIMER INTERRUPT? NO
YES
CORE TIMER INTERRUPT? NO
YES
PROG. TIMER INTERRUPT? NO
YES
PROG. TIMER INTERRUPT? NO
TURN ON SELECTED OSCILLATOR RESET STABILIZATION DELAY TIMER
NON-DISCLOSURE
YES
SIOP INTERRUPT? NO
YES
SIOP INTERRUPT? NO
YES
END OF STABILIZATION DELAY? NO
YES
ANALOG INTERRUPT? NO
YES
ANALOG INTERRUPT? NO
YES TURN ON CPU CLOCK
COP RESET? NO
YES
COP RESET? NO
1. LOAD PC WITH RESET VECTOR OR 2. SERVICE INTERRUPT a. SAVE CPU REGISTERS ON STACK b. SET I BIT IN CCR c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-2. Stop/Wait/Halt Flowchart
General Release Specification 72 Operating Modes MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Operating Modes
6.4.1 Stop Mode The STOP instruction puts the MCU in a mode with the lowest power consumption and affects the MCU as follows: * Turns off the CPU clock and all internal clocks by stopping both the external pin oscillator and the internal low-power oscillator. The selection of the oscillator by the OM1 and OM2 bits in the ISCR is not affected. The stopped clocks turn off the COP watchdog, the core timer, the programmable timer, the analog subsystem, and the SIOP. Removes any pending core timer interrupts by clearing the core timer interrupt flags (CTOF and RTIF) in the core timer status and control register (CTSCR) Disables any further core timer interrupts by clearing the core timer interrupt enable bits (CTOFE and RTIE) in the CTSCR Removes any pending programmable timer interrupts by clearing the timer interrupt flags (ICF, OCF, and TOF) in the timer status register (TSR) Disables any further programmable timer interrupts by clearing the timer interrupt enable bits (ICIE, OCIE, and TOIE) in the timer control register (TCR) Enables external interrupts via the IRQ pin by setting the IRQE bit in the IRQ status and control register (ISCR). External interrupts are also enabled via the PA0 through PA3 pins, if the port A interrupts are enabled by the port A interrupt mask option. Enables interrupts in general by clearing the I bit in the condition code register
*
* *
*
*
*
The STOP instruction does not affect any other bits, registers, or I/O lines. These conditions bring the MCU out of stop mode: * An external interrupt signal on the IRQ pin -- A high-to-low transition on the IRQ pin loads the program counter with the contents of locations $1FFA and $1FFB.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Operating Modes
General Release Specification 73
NON-DISCLOSURE
AGREEMENT
REQUIRED
Operating Modes REQUIRED
* An external interrupt signal on a port A external interrupt pin -- If selected by a mask option, a low-to-high transition on a PA3-PA0 pin loads the program counter with the contents of locations $1FFA and $1FFB. External reset -- A logic zero on the RESET pin resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF.
*
AGREEMENT
When the MCU exits stop mode, processing resumes after a stabilization delay of 16 or 4064 internal bus cycles, depending on the selection of the oscillator startup delay mask option.
NOTE:
Execution of the STOP instruction without using the mask option to make it a HALT instruction will cause the oscillators to stop, and, therefore, disable the COP watchdog timer. If the COP watchdog timer is to be used, stop mode should be changed to halt mode as described in 6.4.3 Halt Mode.
6.4.2 Wait Mode The WAIT instruction puts the MCU in a low-power wait mode which consumes more power than the stop mode and affects the MCU as follows: * * * Enables interrupts by clearing the I bit in the condition code register Enables external interrupts by setting the IRQE bit in the IRQ status and control register Stops the CPU clock which drives the address and data buses, but allows the selected oscillator to continue to clock the core timer, programmable timer, analog subsystem, and SIOP
NON-DISCLOSURE
The WAIT instruction does not affect any other bits, registers, or I/O lines.
General Release Specification 74 Operating Modes
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Operating Modes
These conditions restart the CPU bus clock and bring the MCU out of wait mode: * An external interrupt signal on the IRQ pin -- A high-to-low transition on the IRQ pin loads the program counter with the contents of locations $1FFA and $1FFB. An external interrupt signal on a port A external interrupt pin -- If selected by a mask option, a low-to-high transition on a PA3-PA0 pin loads the program counter with the contents of locations $1FFA and $1FFB. A core timer interrupt -- A core timer overflow or a real-time interrupt loads the program counter with the contents of locations $1FF8 and $1FF9. A programmable timer interrupt -- A programmable timer interrupt driven by an input capture, output compare, or timer overflow loads the program counter with the contents of locations $1FF6 and $1FF7. An SIOP interrupt -- An SIOP interrupt driven by the completion of transmitted or received 8-bit data loads the program counter with the contents of locations $1FF4 and $1FF5. An analog subsystem interrupt -- An analog subsystem interrupt driven by a voltage comparison loads the program counter with the contents of locations $1FF2 and $1FF3. A COP watchdog reset -- A timeout of the COP watchdog resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF. Software can enable real-time interrupts so that the MCU can periodically exit the wait mode to reset the COP watchdog. An external reset -- A logic zero on the RESET pin resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF.
*
*
*
*
*
*
When the MCU exits wait mode, there is no delay before code executes; however, a delay does occur when exiting stop or halt modes.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Operating Modes
General Release Specification 75
NON-DISCLOSURE
*
AGREEMENT
REQUIRED
Operating Modes REQUIRED
6.4.3 Halt Mode The STOP instruction puts the MCU in halt mode if selected by the stop mask option. Halt mode is identical to wait mode, except that a variable recovery delay occurs when the MCU exits halt mode. A recovery time of from 1 to 16 or from 1 to 4064 internal bus cycles can be selected by the oscillator startup delay mask option. If the STOP instruction has been selected by the stop mask option to put the MCU in halt mode, then the COP watchdog cannot be turned off inadvertently by a STOP instruction.
AGREEMENT
6.4.4 Data-Retention Mode In the data-retention mode, the MCU retains RAM contents and CPU register contents at VDD voltages as low as 2.0 Vdc. The data retention feature allows the MCU to remain in a low-power consumption state during which it retains data, but the CPU cannot execute instructions. To put the MCU in the data retention mode: 1. Drive the RESET pin to a logic zero. 2. Lower the VDD voltage. The RESET pin must remain low continuously during data retention mode. To take the MCU out of the data retention mode: 1. Return VDD to normal operating voltage. 2. Return the RESET pin to a logic one.
NON-DISCLOSURE
General Release Specification 76 Operating Modes
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 7. Parallel Input/Output
7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . .80 7.3.3 Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.3.4 Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.3.5 Port A Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . .85 7.4.3 Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.4.4 Port B Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.4.5 PB0, PBI, PB2, and PB3 Logic . . . . . . . . . . . . . . . . . . . . . .87 7.4.6 PB4/AN4/TCMP/CMP1 Logic . . . . . . . . . . . . . . . . . . . . . . .89 7.4.7 PB5/SDO Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.4.8 PB6/SDI Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.4.9 PB7/SCK Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.5 Port C (MC68HC05JP6 Only). . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .100 7.5.3 Port C Pulldown Devices. . . . . . . . . . . . . . . . . . . . . . . . . .100 7.5.4 Port C Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.6 Port Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 77
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED 7.2 Introduction
The MC68HC05JJ6 has 14 bidirectional I/O pins which form two parallel I/O ports, A and B. The MC68HC05JP6 has 22 bidirectional I/O pins which form three parallel I/O ports, A, B and C. Each I/O pin is programmable as an input or an output. The contents of the data direction registers determine the data direction of each of the I/O pins. All I/O pins have software programmable pulldown devices which can be enabled or disabled by the software pulldown inhibit mask option.
AGREEMENT
7.3 Port A
Port A is a 6-bit, general-purpose bidirectional I/O port with these features: * * * * Individual programmable pulldown devices High current sinking capability on all port A pins with a maximum of 15 mA per pin or a total of 40 mA for all six pins High current sourcing capability on all port A pins with a maximum of 5 mA per pin or a total of 20 mA for all six pins External interrupt capability (pins PA3-PA0)
NON-DISCLOSURE
General Release Specification 78 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
7.3.1 Port A Data Register The port A data register contains a bit for each of the port A pins. When a port A pin is programmed to be an output, the state of its data register bit determines the state of the output pin. When a port A pin is programmed to be an input, reading the port A data register returns the logic state of the pin. The upper two bits of the port A data register will always read as logical zeros.
$0000 Read: Write: Reset: Alternate: = Unimplemented Unaffected by Reset KYBD3 KYBD2 KYBD1 KYBD0 Bit 7 0 6 0 PA5 PA4 PA3 PA2 PA1 PA0 5 4 3 2 1 Bit 0
Figure 7-1. Port A Data Register (PORTA) PA5-PA0 -- Port A Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in the port A data direction register (DDRA). Reset has no effect on port A data.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 79
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED
7.3.2 Data Direction Register A The contents of the port A data direction register (DDRA) determine whether each port A pin is an input or an output. Writing a logic one to a DDRA bit enables the output buffer for the associated port A pin. A DDRA bit set to a logic one also disables the pulldown device for that pin. Writing a logic zero to a DDRA bit disables the output buffer for the associated port A pin. The upper two bits always read as logical zeros. A reset initializes all DDRA bits to logic zeros, configuring all port A pins as inputs and disabling the voltage comparators from driving PA4 or PA5.
$0004 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 0 6 0 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 5 4 3 2 1 Bit 0
AGREEMENT
= Unimplemented
Figure 7-2. Data Direction Register A (DDRA) DDRA5-DDRA0 -- Port A Data Direction Bits These read/write bits control port A data direction. Reset clears the DDRA5-DDRA0 bits. 1 = Corresponding port A pin configured as output and pulldown device disabled 0 = Corresponding port A pin configured as input
NON-DISCLOSURE
General Release Specification 80
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Parallel Input/Output Freescale Semiconductor
Parallel Input/Output
7.3.3 Pulldown Register A All port A pins can have software programmable pulldown devices enabled or disabled by a mask option. When enabled these pulldowns can sink approximately 100 A. These pulldown devices are controlled by the write-only pulldown register A (PDRA) shown in Figure 7-3. Clearing the PDIA5-PDIA0 bits in the PDRA turns on the pulldown devices if the port A pin is an input. Reading the PDRA returns undefined results since it is a write-only register. On the MC68HC05JJ6, the PDRA contains two pulldown control bits (PDICH and PDICL) for port C. Reset clears the PDIA5-PDIA0, PDICH and PDICL bits, which turns on all the port A and port C pulldown devices.
$0010 Read: Write: Reset: PDICH 0 PDICL 0 PDIA5 0 PDIA4 0 PDIA3 0 PDIA2 0 PDIA1 0 PDIA0 0 Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA) PDICH -- Upper Port C Pulldown Inhibit Bits (MC68HC05JP6) Writing to this write-only bit controls the port C pulldown devices on the upper four bits (PC4:PC7). Reading these pulldown register A bits returns undefined data. Reset clears bit PDICH. 1 = Upper four port C pins pulldown devices turned off 0 = Upper four port C pins pulldown devices turned on if pin has been programmed by the DDRC to be an input PDICL -- Lower Port C Pulldown Inhibit Bits (MC68HC05JP6) Writing to this write-only bit controls the port C pulldown devices on the lower four bits (PC0:PC3). Reading these pulldown register A bits returns undefined data. Reset clears bit PDICL. 1 = Lower four port C pins pulldown devices turned off 0 = Lower four port C pins pulldown devices turned on if pin has been programmed by the DDRC to be an input
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 81
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED
PDIA5-PDIA0 -- Port A Pulldown Inhibit Bits Writing to these write-only bits controls the port A pulldown devices. Reading these pulldown register A bits returns undefined data. Reset clears bits PDIA5-PDIA0. 1 = Corresponding port A pin pulldown device turned off 0 = Corresponding port A pin pulldown device turned on if pin has been programmed by the DDRA to be an input
AGREEMENT
7.3.4 Port A External Interrupts A mask option enables the PA3-PA0 pins to serve as external interrupt pins in addition to the IRQ pin. The active interrupt state for the PA3-PA0 pins is a logic one or a rising edge. Another mask option also determines whether external interrupt inputs are edge-sensitive only or both edge- and level-sensitive. Port A interrupts are also interactive with each other and the IRQ pin as described in 4.6 External Interrupts.
NOTE:
When testing for external interrupts, the BIH and BIL instructions test the voltage on the IRQ pin, not the state of the internal IRQ signal. Therefore, BIH and BIL cannot test the port A external interrupt pins.
NON-DISCLOSURE
7.3.5 Port A Logic When a PA0:PA5 pin is programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. When a PA0:PA5 pin is programmed as an input, reading the port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its DDR bit. Figure 7-4 shows the I/O logic of PA0:PA5 pins of port A. The data latch can always be written, regardless of the state of its DDR bit. Table 7-1 summarizes the operations of the port A pins.
General Release Specification 82 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
READ $0004 WRITE $0004 DATA DIRECTION REGISTER A BIT DDRAx
EXTERNAL INTERRUPT REQUEST (PA0:PA3)
R
INTERNAL DATA BUS
WRITE $0000
PORT A DATA REGISTER BIT PAx
PAx 15 mA SINK 5 mA SOURCE CAPABILITY
READ $0000 WRITE $0010 PULLDOWN REGISTER A BIT PDIAx
R RESET
100 A PULLDOWN DEVICE
PULLDOWN INHIBIT MASK OPTION (ENABLE = 0)
Figure 7-4. Port A I/O Circuit
Table 7-1. Port A Pin Functions
Port A Pin(s) PA0 PA1 PA2 PA3 PA4 PA5 Mask Option Pulldown Inhibit 0 0 1 X Port A PDIAn 0 1 X X DDRAn* 0 0 0 1 PORTA Access (Pin or Data Register) Read PIN PIN PIN DATA Write DATA DATA DATA DATA Result on Port A Pins Pulldown ON OFF OFF OFF Pin PAn IN PAn IN PAn IN PAn OUT
* DDRA can always be read or written. X = Don't Care
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 83
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED 7.4 Port B
Port B is an 8-bit, general-purpose bidirectional I/O port with the following features: * * * * Programmable pulldown devices PB0 through PB4 shared with the analog subsystem PB3 and PB4 shared with the 16-bit programmable timer PB4 can be driven directly by the output of comparator 1 PB5 through PB7 shared with the simple serial interface (SIOP) High current sinking capability to 15 mA on the PB4 pin High current sourcing capability to 5 mA on the PB4 pin
AGREEMENT
* * *
7.4.1 Port B Data Register The port B data register contains a bit for each of the port B pins. When a port B pin is programmed to be an output, the state of its data register bit determines the state of the output pin. When a port B pin is programmed to be an input, reading the port B data register returns the logic state of the pin. Reset has no effect on port B data.
$0001 Read: PB7 Write: Reset: Alternate: Alternate: Alternate: SCK SCK SCK SDI SDI SDI SDO SDO SDO Unaffected by Reset AN4 TCMP CMP1 AN3 TCAP TCAP AN2 AN1 AN0 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Bit 7 6 5 4 3 2 1 Bit 0
NON-DISCLOSURE
Figure 7-5. Port B Data Register (PORTB) PB0-PB7 -- Port B Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data.
General Release Specification 84 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
7.4.2 Data Direction Register B The contents of the port B data direction register (DDRB) determine whether each port B pin is an input or an output. Writing a logic one to a DDRB bit enables the output buffer for the associated port B pin. A DDRB bit set to a logic one also disables the pulldown device for that pin. Writing a logic zero to a DDRB bit disables the output buffer for the associated port B pin. A reset initializes all DDRB bits to logic zeros, configuring all port B pins as inputs.
$0005 Read: DDRB7 Write: Reset: 0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Bit 7 6 5 4 3 2 1 Bit 0
Figure 7-6. Data Direction Register B (DDRB) DDRB7-DDRB0 -- Port B Data Direction Bits These read/write bits control port B data direction. Reset clears the bits DDRB7-DDRB0. 1 = Corresponding port B pin configured as output and pulldown device disabled 0 = Corresponding port B pin configured as input
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 85
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED
7.4.3 Pulldown Register B All port B pins can have software programmable pulldown devices enabled or disabled by the software pulldown inhibit mask option. When enabled these pulldowns can sink approximately 100 A. These pulldown devices are controlled by the write-only pulldown register B (PDRB) shown in Figure 7-7. Clearing the PDIB7-PDIB0 bits in the PDRB turns on the pulldown devices if the port B pin is an input. Reading the PDRB returns undefined results since it is a write-only register. Reset clears the PDIB7-PDIB0 bits, which turns on all the port B pulldown devices.
$0011 Read: Write: Reset: PDIB7 0 PDIB6 0 PDIB5 0 PDIB4 0 PDIB3 0 PDIB2 0 PDIB1 0 DIB0 0 Bit 7 6 5 4 3 2 1 Bit 0
AGREEMENT
= Unimplemented
Figure 7-7. Pulldown Register B (PDRB) PDIB7-PDIB0 -- Port B Pulldown Inhibit Bits Writing to these write-only bits controls the port B pulldown devices. Reading these pulldown register B bits returns undefined data. Reset clears bits PDIB7-PDIB0. 1 = Corresponding port B pin pulldown device turned off 0 = Corresponding port B pin pulldown device turned on if pin has been programmed by the DDRB to be an input
NON-DISCLOSURE
7.4.4 Port B Logic All port B pins have the general I/O port logic similar to port A; but they also share this function with inputs or outputs from other modules, which are also attached to the pin itself or override the general I/O function. PB0, PB1, PB2, and PB3 simply share their inputs with another module. PB4, PB5, PB6, and PB7 will have their operation altered by outputs or controls from other modules.
General Release Specification 86 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
7.4.5 PB0, PBI, PB2, and PB3 Logic The typical I/O logic shown in Figure 7-8 is used for PB0, PB1, PB2, and PB3 pins of port B. When these port B pins are programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. When these port B pins are programmed as an input, reading the port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its DDRB bit. The operations of the PB0:PB3 pins are summarized in Table 7-2.
READ $0005 WRITE $0005 DATA DIRECTION REGISTER B BIT DDRBx
ANALOG SUBSYSTEM, AND PROGRAMMABLE TIMER INPUT CAPTURE (PINS PB0, PB1, PB2, PB3)
R
WRITE $0001 INTERNAL DATA BUS
PORT BDATA REGISTER BIT PBx
PBx
READ $0001 WRITE $0011 PULLDOWN REGISTER B BIT PDIBx 100 A PULLDOWN DEVICE
R RESET
PULLDOWN INHIBIT MASK OPTION (ENABLE = 0)
Figure 7-8. PB0:PB3 Pin I/O Circuit
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 87
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED
The PB0:PB3 pins share their inputs with another module. When using the other attached module, these conditions must be observed: 1. If the DDRB configures the pin as an output, then the port data register can provide an output which may conflict with any external input source to the other module. The pulldown device will be disabled in this case. 2. If the DDRB configures the pin as an input, then reading the port data register will return the state of the input in terms of the digital threshold for that pin. (Analog inputs will default to logic states.) 3. If DDRB configures the pin as an input and the pulldown device is activated for a pin, it will also load the input to the other module. 4. If interaction between the port logic and the other module is not desired, the pin should be configured as an input by clearing the appropriate DDRB bit and disabling the input pulldown device by clearing the appropriate PDRB bit (or by disabling programmable pulldowns with a mask option).
NON-DISCLOSURE
General Release Specification 88 Parallel Input/Output
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
7.4.6 PB4/AN4/TCMP/CMP1 Logic The PB4/AN4/TCMP/CMP1 pin can be used as a simple I/O port pin, be controlled by the OLVL bit from the output compare function of the 16-bit programmable timer, or be controlled directly by the output of comparator 1 as shown in Figure 7-9. The PB4 data, the programmable timer OLVL bit, and the output of comparator 1 are all ORed together to drive the pin. Also, the analog subsystem input channel 4 multiplexer is connected directly to this pin. The operations of the PB4 pin are summarized in Table 7-2.
READ $0005 WRITE $0005 DATA DIRECTION REGISTER B BIT DDRB4
ANALOG SUBSYSTEM INPUT AN4 AND TIMER OUTPUT COMPARE
R
INTERNAL DATA BUS
WRITE $0001
PORT BDATA REGISTER BIT PB4 OLVL TIMER OUTPUT COMPARE CMP1 COMPARATOR 1 OUT
PB4 AN4 TCMP 15 mA SINK 5 mA SOURCE CAPABILITY
READ $0001
WRITE $0011 R RESET
PULLDOWN REGISTER B BIT PDIB4
100 A PULLDOWN DEVICE
COMP 1 OUTPUT MASK OPTION (ENABLE = 1)
PULLDOWN INHIBIT MASK OPTION (ENABLE = 0)
Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 89
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED
When using the PB4/AN4/TCMP/CMP1 pin, these interactions must be noted: 1. If the OLVL timer output compare function is the required output function, then the DDRB4 bit must be set, the PB4 data bit must be cleared and the comparator output feature disabled by a mask option. The PB4/AN4/TCMP/CMP1 pin becomes an output which follows the state of the OLVL bit. The pulldown device will be disabled in this case. The analog subsystem would not normally use this pin as an analog input in this case. 2. If the PB4 data bit is the required output function, then the DDRB4 bit must be set, the OLVL bit in the TCR must be cleared and the comparator output feature disabled by a mask option. The pulldown device will be disabled in this case. The analog subsystem would not normally use this pin as an analog input in this case. 3. If the comparator 1 output is the desired output function, then the PB4 data bit must be cleared, the DDRB4 bit must be set, the OLVL bit in the TCR must be cleared, and the comparator output feature must be enabled by the analog options mask option. The PB4/AN4/TCMP/CMP1 pin becomes an output which follows the state of the OLVL bit. The pulldown device will be disabled in this case. The analog subsystem would not normally use this pin as an analog input in this case. 4. If the PB4 pin is to be an input to the analog subsystem or a digital input, then the DDRB4 bit must be cleared. In this case, the PB4 pin can still be read; but the voltage present will be returned as a binary value. Depending on the external application, the PB4 pulldown may also be disabled by setting the PDIB4 pulldown inhibit bit. In this case, both the digital and analog functions connected to this pin can be utilized. .
NON-DISCLOSURE
AGREEMENT
General Release Specification 90
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Parallel Input/Output Freescale Semiconductor
Parallel Input/Output
Table 7-2. Port B Pin Functions - PB0:PB4
Control Bits Comparator 1 Port B Pin CMP1 Timer Mask Option Inhibit Pulldown 0 X X X X 0 1 X 0 X X X X 0 1 PB4 X X 0 X 1 X 0 1 X 1 0 1 1 X 1 0 0 0 1 X X X X X X Port B PDIBn DDRBn* 0 1 X X 0 1 X X X X X X 0 0 0 1 0 0 0 1 1 1 1 1 PORTB Access (Pin or Data Register) Read PIN PIN PIN DATA PIN PIN PIN DATA DATA DATA 1 1 Write DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA Result on Port B Pins
Mask COE1 Option OLVL Comp Output
Pulldown ON OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF
Pin PBn IN PBn IN PBn IN PBn OUT PB4 IN PB4 IN PB4 IN PB4 OUT PB4 OUT PB4 OUT 1 1
* DDRB can always be read or written. X = Don't Care
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 91
NON-DISCLOSURE
AGREEMENT
PB0 PB1 PB2 PB3
REQUIRED
Parallel Input/Output REQUIRED
7.4.7 PB5/SDO Logic The PB5/SDO pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as shown in Figure 7-10. The operations of the PB5 pin are summarized in Table 7-3.
SERIAL DATA OUT (SDO) SERIAL ENABLE (SPE) READ $0005 VDD
AGREEMENT
WRITE $0005 DATA DIRECTION REGISTER B BIT DDRB5
R INTERNAL DATA BUS
WRITE $0001
PORT B DATA REGISTER BIT PB5
PB5 SDO
READ $0001 WRITE $0011 PULLDOWN REGISTER B BIT PDIB5
R RESET
100 A PULLDOWN DEVICE
NON-DISCLOSURE
PULLDOWN INHIBIT MASK OPTION (ENABLE = 0)
Figure 7-10. PB5/SDO Pin I/O Circuit
General Release Specification 92 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
When using the PB5/SDO pin, these interactions must be noted: 1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB5/SDO pin buffer to be enabled and to be driven by the serial data output (SDO) from the SIOP. The pulldown device will be disabled in this case. 2. If the SIOP function is in control of the PB5/SDO pin, the DDRB5 and PB5 data register bits are still accessible to the CPU and can be altered or read without affecting the SIOP functionality. However, if the DDRB5 bit is cleared, reading the PB5 data register will return the current state of the PB5/SDO pin. 3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored in the DDRB5, PDIB5, and PB5 register bits will then control the PB5/SDO pin. 4. If the PB5/SDO pin is to be a digital input, then both the SPE bit in the SCR and the DDRB5 bit must be cleared. Depending on the external application, the pulldown device may also be disabled by setting the PDIB5 pulldown inhibit bit. 5. If the PB5/SDO pin is to be a digital output, then the SPE bit in the SCR must be cleared and the PDIB5 bit must be set. The pulldown device will be disabled in this case.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 93
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED
7.4.8 PB6/SDI Logic The PB6/SDI pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as shown in Figure 7-11. The operations of PB6/SDI pin are summarized in Table 7-3.
SERIAL DATA IN (SDI) SERIAL ENABLE (SPE) READ $0005 WRITE $0005
AGREEMENT
R
DATA DIRECTION REGISTER B BIT DDRB6
INTERNAL DATA BUS
WRITE $0001
PORT B DATA REGISTER BIT PB6
PB6 SDI
READ $0001 WRITE $0011 PULLDOWN REGISTER B BIT PDIB6
R RESET
100 A PULLDOWN DEVICE
NON-DISCLOSURE
PULLDOWN INHIBIT MASK OPTION (ENABLE = 0)
Figure 7-11. PB6/SDI Pin I/O Circuit
General Release Specification 94 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
When using the PB6/SDI pin, these interactions must be noted: 1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB6/SDI pin buffer to be disabled to allow the PB6/SDI pin to act as an input that feeds the serial data input (SDI) of the SIOP. The pulldown device is disabled in this case. 2. If the SIOP function is in control of the PB6/SDI pin, the DDRB6 and PB6 data register bits are still accessible to the CPU and can be altered or read without affecting the SIOP functionality. However, if the DDRB6 bit is cleared, reading the PB6 data register will return the current state of the PB6/SDI pin. 3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored in the DDRB6, PDIB6, and PB6 register bits will then control the PB6/SDI pin. 4. If the PB6/SDI pin is to be a digital input, then both the SPE bit in the SCR and the DDRB6 bit must be cleared. Depending on the external application, the pulldown device may also be disabled by setting the PDIB6 pulldown inhibit bit. 5. If the PB6/SDI pin is to be a digital output, then the SPE bit in the SCR must be cleared and the DDRB6 bit must be set. The pulldown device will be disabled in this case.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 95
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED
7.4.9 PB7/SCK Logic The PB7/SCK pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as shown in Figure 7-12. The operations of the PB7/SCK pin are summarized in Table 7-3.
SERIAL DATA CLOCK (SCK) CLOCK SOURCE (MSTR) SERIAL ENABLE (SPE)
AGREEMENT
READ $0005 WRITE $0005
INTERNAL DATA BUS
R
DATA DIRECTION REGISTER B BIT DDRB7
WRITE $0001
PORT B DATA REGISTER BIT PB7
PB7 SCK
READ $0001 WRITE $0011 PULLDOWN REGISTER B BIT PDIB7
NON-DISCLOSURE
R RESET
100 A PULLDOWN DEVICE
PULLDOWN INHIBIT MASK OPTION (ENABLE = 0)
Figure 7-12. PB7/SCK Pin I/O Circuit
General Release Specification 96 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
When using the PB7/SCK pin, these interactions must be noted: 1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB7/SCK pin buffer to be controlled by the MSTR control bit in the SCR. The pulldown device is disabled in these cases. a. If the MSTR bit is set, then the PB7/SCK pin buffer will be enabled and driven by the serial data clock (SCK) from the SIOP. b. If the MSTR bit is clear, then the PB7/SCK pin buffer will be disabled, allowing the PB7/SCK pin to drive the serial data clock (SCK) into the SIOP. 2. If the SIOP function is in control of the PB7/SCK pin, the DDRB7 and PB7 data register bits are still accessible to the CPU and can be altered or read without affecting the SIOP functionality. However, if the DDRB7 bit is cleared, reading the PB7 data register will return the current state of the PB7/SCK pin. 3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored in the DDRB7, PDIB7, and PB7 register bits will then control the PB7/SCK pin. 4. If the PB7/SCK pin is to be a digital input, then both the SPE bit in the SCR and the DDRB7 bit must be cleared. Depending on the external application, the pulldown device may also be disabled by setting the PDIB7 pulldown inhibit bit. 5. If the PB7/SCK pin is to be a digital output, then the SPE bit in the SCR must be cleared and the DDRB7 bit must be set. The pulldown device will be disabled when the pin is set as an output.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 97
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED
Table 7-3. Port B Pin Functions - PB5:PB7
Control Bits Port B Pin SPE SIOP MSTR Mask Option Inhibit Pulldown 0 0 X 0 1 X 1 X X 0 0 PB6 X 0 1 X 1 X X 0 0 X 0 1 X 0 1 1 X X X Port B PDIBn 0 1 X X X 0 1 X X X 0 1 X X X DDRBn* 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 PORTB Access (Pin or Data Register) Read PIN PIN PIN DATA SDO DATA PIN PIN PIN DATA SDI DATA PIN PIN PIN DATA SCK DATA SCK DATA Write DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA Result on Port B Pins Pulldown ON OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF Pin PB5 IN PB5 IN PB5 IN PB5 OUT SDO OUT SDO OUT PB6 IN PB6 IN PB6 IN PB6 OUT SDI IN SDI IN PB7 IN PB7 IN PB7 IN PB7 OUT SCK IN SCK IN SCK OUT SCK OUT
NON-DISCLOSURE
AGREEMENT
PB5
PB7
* DDRB can always be read or written. X = Don't Care
General Release Specification 98 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
7.5 Port C (MC68HC05JP6 Only)
Port C is an 8-bit, general-purpose bidirectional I/O port with individual programmable pulldown devices. It is only available on the 28-pin MC68HC05JP6 device. Port C has these features: * * * Independent high and low nibble programmable pulldown devices High-current sinking capability on all port C pins with a maximum of 15 mA per pin or a total of 60 mA for all eight pins High-current sourcing capability on all port C pins with a maximum of 5 mA per pin or a total of 30 mA for all eight pins
7.5.1 Port C Data Register The port C data register contains a bit for each of the port C pins. When a port C pin is programmed to be an output, the state of its data register bit determines the state of the output pin. When a port C pin is programmed to be an input, reading the port C data register returns the logic state of the pin.
$0002 Read: PC7 Write: Reset: Unaffected by Reset PC6 PC5 PC4 PC3 PC2 PC1 PC0 Bit 7 6 5 4 3 2 1 Bit 0
Figure 7-13. Port C Data Register (PORTC) PC7-PC0 -- Port C Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in the port C data direction register (DDRC). Reset has no effect on port C data.
NOTE:
For 20-pin devices, port C pins are not available. However, port C logic is present on the MCU. Therefore, port C must be enabled as an output or pulldowns must be enabled. This is to prevent floating input pins.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 99
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output REQUIRED
7.5.2 Data Direction Register C The contents of the port C data direction register (DDRC) determine whether each port C pin is an input or an output. Writing a logic one to a DDRC bit enables the output buffer for the associated port C pin. A DDRC bit set to a logic one also disables the pulldown device for that pin. Writing a logic zero to a DDRC bit disables the output buffer for the associated port C pin. A reset initializes all DDRC bits to logic zeros, configuring all port C pins as inputs.
$0006 Read: DDRC7 Write: Reset: 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 Bit 7 6 5 4 3 2 1 Bit 0
AGREEMENT
Figure 7-14. Data Direction Register C (DDRC) DDRC7-DDRC0 -- Port C Data Direction Bits These read/write bits control port C data direction. Reset clears the DDRC7-DDRC0 bits. 1 = Corresponding port C pin configured as output and pulldown device disabled 0 = Corresponding port C pin configured as input
NON-DISCLOSURE
7.5.3 Port C Pulldown Devices All port C pins can have software programmable pulldown devices enabled or disabled by the software pulldown inhibit mask option. When enabled these pulldowns can sink approximately 100 A. These pulldown devices are controlled by the write-only pulldown register A (PDRA) shown in Figure 7-3. PDICH controls the upper four pins (PC7:PC4) and PDICL controls the lower four pins (PC3:PC0). Clearing the PDICH or PDICL bits in the PDRA turns on the pulldown devices if the port C pin is an input. Reading the PDRA returns undefined results since it is a write-only register. Reset clears the PDICH and PDICL bits, which turns on all the port C pulldown devices.
General Release Specification 100 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Parallel Input/Output
7.5.4 Port C Logic Figure 7-15 shows the I/O logic of port C. When a port C pin is programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. When a port C pin is programmed as an input, reading the port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its DDR bit. Table 7-4 summarizes the operations of the port C pins.
READ $0006 WRITE $0006 DATA DIRECTION REGISTER C BIT DDRCx
R
WRITE $0002
PORT C DATA REGISTER BIT PCx
PCx 15 mA SINK 5 mA SOURCE CAPABILITY
READ $0002 WRITE $0010 PULLDOWN REGISTER A BIT PDICx
R RESET
100 A PULLDOWN DEVICE
PULLDOWN INHIBIT MASK OPTION (ENABLE = 0)
Figure 7-15. Port C I/O Circuit
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Parallel Input/Output
General Release Specification 101
NON-DISCLOSURE
AGREEMENT
INTERNAL DATA BUS
REQUIRED
Parallel Input/Output REQUIRED
Table 7-4. Port C Pin Functions (MC68HC05JP6)
Control Bits Port C Pin(s) Mask Option Pulldown Inhibit 0 0 1 X 0 0 1 X Port C PDICH X X X X 0 1 X X PDICL 0 1 X X X X X X DDRCn* 0 0 0 1 0 0 0 1 PORTC Access (Pin or Data Register) Read PIN PIN PIN DATA PIN PIN PIN DATA Write DATA DATA DATA DATA DATA DATA DATA DATA Result on Port C Pins Pulldown ON OFF OFF OFF ON OFF OFF OFF Pin PCn IN PCn IN PCn IN PCn OUT PCn IN PCn IN PCn IN PCn OUT
AGREEMENT
Low Nibble PC0 PC1 PC2 PC3 High Nibble PC4 PC5 PC6 PC7
* DDRC can always be read or written. X = Don't Care
7.6 Port Transitions
Glitches and temporary floating inputs can occur if the control bits regarding each port I/O pin are not performed in the correct sequence. * * Do not use read-modify-write instructions on pulldown register A or B. Avoid glitches on port pins by writing to the port data register before changing data direction register bits from a logic zero to a logic one. Avoid a floating port input by clearing its pulldown register bit before changing its data direction register bit from a logic one to a logic zero. A mask option turns off all port pulldown devices and disables software control of the pulldown devices. Reset has no effect on the pulldown devices if they are not selected by mask option.
NON-DISCLOSURE
*
*
General Release Specification 102 Parallel Input/Output
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 8. Analog Subsystem
8.1 Contents
8.2 8.3 8.4 8.5 8.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Analog Multiplex Register . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Analog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Analog Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 A/D Conversion Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.7 Voltage Measurement Methods . . . . . . . . . . . . . . . . . . . . . . .128 8.7.1 Absolute Voltage Readings . . . . . . . . . . . . . . . . . . . . . . . .129 8.7.1.1 Internal Absolute Reference. . . . . . . . . . . . . . . . . . . . . .129 8.7.1.2 External Absolute Reference . . . . . . . . . . . . . . . . . . . . .130 8.7.2 Ratiometric Voltage Readings. . . . . . . . . . . . . . . . . . . . . .131 8.7.2.1 Internal Ratiometric Reference . . . . . . . . . . . . . . . . . . .131 8.7.2.2 External Ratiometric Reference . . . . . . . . . . . . . . . . . . .131 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 Voltage Comparator Features . . . . . . . . . . . . . . . . . . . . . . . .133 Current Source Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Internal Temperature Sensing Diode Features. . . . . . . . . . . .134 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Port B Interaction with Analog Inputs . . . . . . . . . . . . . . . . . . .135 Port B Pins as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Port B Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 Noise Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
8.2 Introduction
The analog subsystem of the MC68HC05JJ6/MC68HC05JP6 is based on two on-chip voltage comparators and a selectable current charge/discharge function as shown in Figure 8-1.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem General Release Specification 103
NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog Subsystem REQUIRED
PB3/AN3/TCAP OCF ICF VDD PORTB LOGIC PB0 AN0 VDD IDISCHG CP2EN + - INTERNAL TEMPERATURE DIODE INV CP1EN CPIE VDD COMPARATOR INPUT SELECT AND SAMPLE CONTROL COMP2 ICHG CHG CHARGE CURRENT CONTROL LOGIC ATD1 ATD2 ISEN CP2EN
2 TO 1 MUX
TCAP
AGREEMENT
ICEN
$001D ANALOG INTERRUPT
80 K
VREF 80 K
CPF2 ANALOG STATUS REGISTER (ASR) CPF1 CMP2 CMP1 VOFF INTERNAL HC05 BUS
PORTB LOGIC
SAMPLE CAP
NON-DISCLOSURE
PB1 AN1 PORTB LOGIC PB2 AN2 PORTB LOGIC PB3 AN3 TCAP PORTB LOGIC PB4 AN4 TCMP MUX4 VAOFF VSS MUX3 MUX2 CHANNEL SELECT BUS + - INV MUX1 100 MV OFFSET
-+
$001E CP1EN V OFFSET MASK OPTION HOLD DHOLD INV ANALOG MUX REGISTER (AMUX) $0003 DENOTES INTERNAL ANALOG VSS
COMP1
VREF
VREF MUX4 MUX3 MUX2
-+
VSS
PORT B CONTROL LOGIC MUX4 MUX3 MUX2 MUX1
COE1 MASK OPTION
MUX1
Figure 8-1. Analog Subsystem Block Diagram
General Release Specification 104 Analog Subsystem MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
ANALOG CONTROL REGISTER (ACR)
16-BIT PROG. TIMER
TOF
Analog Subsystem
This configuration provides several features: * * Two (2) independent voltage comparators with external access to both inverting and non-inverting inputs One voltage comparator can be connected as a single-slope A/D and the other connected as a single-voltage comparator. The possible single-slope A/D connection provides these features: - A/D conversions can use VDD or an external voltage as a reference with software used to calculate ratiometric or absolute results - Channel access of up to four inputs via multiplexer control with independent multiplexer control allowing mixed input connections - Access to VDD and VSS for calibration - - - - Divide by 2 to extend input voltage range Each comparator can be inverted to calculate input offsets Internal sample and hold capacitor Direct digital output of comparator 1 to the PB4 pin
* * *
Output compare from the 16-bit programmable timer Timer overflow from the 16-bit programmable timer Direct software control via a register bit
The end of the A/D conversion time can be captured by these means: * * * Input capture in the 16-bit programmable timer Interrupt generated by the comparator output Software polling of the comparator output using software loop time
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 105
NON-DISCLOSURE
Voltages are resolved by measuring the time it takes an external capacitor to charge up to the level of the unknown input voltage being measured. The beginning of the A/D conversion time can be started by these means:
AGREEMENT
REQUIRED
Analog Subsystem REQUIRED 8.3 Analog Multiplex Register
The analog multiplex register (AMUX) controls the general interconnection and operation. The control bits in the AMUX are shown in Figure 8-2.
$0003 Read: HOLD Write: Reset: 1 DHOLD 0 INV 0 VREF 0 MUX4 0 MUX3 0 MUX2 0 MUX1 0 Bit 7 6 5 4 3 2 1 Bit 0
AGREEMENT
Figure 8-2. Analog Multiplex Register (AMUX) HOLD, DHOLD These read/write bits control the source connection to the negative input of voltage comparator 2 shown in Figure 8-3. This allows the voltage on the internal temperature sensing diode, the channel selection bus, or the 1:2 divided channel selection bus to charge the internal sample capacitor and to also be presented to comparator 2. The decoding of these sources is given in Table 8-1. During the hold case when both the HOLD and DHOLD bits are clear, the VOFF bit in the analog status register (ASR) can offset the VSS reference on the sample capacitor by approximately 100 mV. This offset source is bypassed whenever the sample capacitor is being charged with either the HOLD or DHOLD bit set. The VOFF bit must be enabled by the analog options mask option. During a reset the HOLD bit is set and the DHOLD bit is cleared, which connects the internal sample capacitor to the channel selection bus. And since a reset also clears the MUX1:MUX4 bits, the channel selection bus will be connected to VSS and the internal sample capacitor will be discharged to VSS following the reset.
NON-DISCLOSURE
NOTE:
When sampling a voltage for later conversion, the HOLD and DHOLD bits should be cleared before making any changes in the MUX channel selection. If the MUX channel and the HOLD/DHOLD are changed on the same write cycle to the AMUX register, the sampled voltage may be altered during the channel switching.
General Release Specification 106 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
VDD
PB0 INTERNAL TEMPERATURE DIODE CHANNEL SELECTION BUS
+ -
COMP2
VSS OFFSET
-+
VOFF MASK OPTION (ENABLE = 1) HOLD DHOLD
Figure 8-3. Comparator 2 Input Circuit Table 8-1. Comparator 2 Input Sources
Case HOLD (AMUX) DHOLD (AMUX) Mask Option Analog Options 0 Hold Sample Voltage 1 0 0 1 1 Yes VOFF (ASR) X 0 Voltage Offset Source To Negative Input of Comparator 2 Sample capacitor connected to comparator 2 negative input; very low leakage current. Sample capacitor connected to comparator 2 negative input; bottom of capacitor offset from VSS by approximately 100 mV, very low leakage current. Signal on channel selection bus is divided by 2 and connected to sample capacitor and comparator 2 negative input Signal on channel selection bus is connected directly to sample capacitor and comparator 2 negative input. Internal temperature sensing diode connected directly to sample capacitor and comparator 2 negative input.
No
Divided Input Direct Input Internal Temperature Diode
X = Don't Care
0
1
X
X
No
1
0
X
X
No
1
1
X
X
No
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 107
NON-DISCLOSURE
AGREEMENT
SAMPLE CAP
80 K
REQUIRED
80 K
Analog Subsystem REQUIRED
INV This is a read/write bit that controls the relative polarity of the inherent input offset voltage of the voltage comparators. This bit allows voltage comparisons to be made with both polarities and then averaged together by taking the sum of the two readings and then dividing by 2 (logical shift right). The polarity of the input offset is reversed by interchanging the internal voltage comparator inputs while also inverting the comparator output. This interchange does not alter the action of the voltage comparator output with respect to its port pins. That is, the output will only go high if the voltage on the positive input (PB2 pin for comparator 1 and PB0 pin for comparator 2) is above the voltage on the respective negative input (PB3 pin for comparator 1 and PB1 pin for comparator 2). This is shown schematically in Figure 8-4. This bit is cleared by a reset of the device. 1 = Voltage comparators internally inverted 0 = Voltage comparators not internally inverted
NON-DISCLOSURE
AGREEMENT
V+
VIO
RISE WHEN V+ > V-
V+
VIO
RISE WHEN V+ > V-
+ COMP -
+ COMP -
V-
INV = 0
V-
INV = 1
Figure 8-4. INV Bit Action
NOTE:
The effect of changing the state of the INV bit is to only change the polarity of the input offset voltage. It does not change the output phase of the CPF1 or CPF2 flags with respect to the external port pins.
General Release Specification 108 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
NOTE:
Either comparator may generate an output flag when the inputs are exchanged due to a change in the state of the INV bit. It is therefore recommended that the INV bit not be changed while waiting for a comparator flag. Further, any changes to the state of the INV bit should be followed by writing a logical one to both the CPFR1 and CPFR2 bits to clear any extraneous CPF1 or CPF2 flags that may have occurred. VREF This read/write bit connects the channel select bus to VDD for making a reference voltage measurement. It cannot be selected if any of the other input sources to the channel select bus are selected as shown in Table 8-2. This bit is cleared by a reset of the device. 1 = Channel select bus is connected to VDD if all MUX1:MUX4 are cleared. 0 = Channel select bus cannot be connected to VDD. MUX1:MUX4 These are read/write bits that connect the analog subsystem pins to the channel select bus and voltage comparator 2 for purposes of making a voltage measurement. They can be selected individually or combined with any of the other input sources to the channel select bus as shown in Table 8-2.
NOTE:
The VAOFF voltage source shown in Figure 8-1 depicts a small offset voltage generated by the total chip current passing through the package bond wires and lead frame that are attached to the single VSS pin. This offset raises the internal VSS reference (AVSS) in the analog subsystem with respect to the external VSS pin. Turning on the VSS MUX to the channel select bus connects it to this internal AVSS reference line. When making A/D conversions, this AVSS offset gets placed on the external ramping capacitor since the discharge device on the PB0/AN0 pin discharges the external capacitor to the internal AVSS line. Under these circumstances, the positive input (+) to comparator 2 will always be higher than the negative input (-) until the negative input reaches the AVSS offset voltage plus any offset in comparator 2. Therefore, input voltages cannot be resolved if they are less than the sum of the AVSS offset and the comparator offset because they will always yield a low output from the comparator.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 109
NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog Subsystem REQUIRED
Table 8-2. Channel Select Bus Combinations
Analog Multiplex Register VREF 0 X X X X X X X X X X X X MUX4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 MUX3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 MUX2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 MUX1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDD --------------------------------ON Channel Select Bus Connected to: PB4/AN4/ TCMP ----------------ON ON ON ON ON ON ON ON --PB3/AN3/ TCAP --------ON ON ON ON --------ON ON ON ON --PB2/AN2 ----ON ON ----ON ON ----ON ON ----ON ON --PB1/AN1 --ON --ON --ON --ON --ON --ON --ON --ON --VSS ON ---------------------------------
NON-DISCLOSURE
AGREEMENT
X X X 1
X = Don't Care - - - = High Impedance
General Release Specification 110 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
8.4 Analog Control Register
The analog control register (ACR) controls the power-up, interrupt, and flag operation. The analog subsystem draws about 500 A of current while it is operating. The resulting power consumption can be reduced by powering down the analog subsystem when not in use. This can be done by clearing three enable bits (ISEN, CP1EN, and CP2EN) in the ACR at $001D. Since these bits are cleared following a reset, the voltage comparators and the charge current source will be powered down following a reset of the device. The control bits in the ACR are shown in Figure 8-5. All the bits in this register are cleared by a reset of the device.
$001D Read: Write: Reset: Bit 7 CHG 0 6 ATD2 0 5 ATD1 0 4 ICEN 0 3 CPIE 0 2 CP2EN 0 1 CP1EN 0 Bit 0 ISEN 0
Figure 8-5. Analog Control Register (ACR) CHG The CHG enable bit allows direct control of the charge current source and the discharge device; and also reflects the state of the discharge device. This bit is cleared by a reset of the device. 1 = If the ISEN bit is also set, the charge current source is sourcing current out of the PB0/AN0 pin. Writing a logical one enables the charging current out of the PB0/AN0 pin. 0 = The discharge device is sinking current into the PB0/AN0 pin. Writing a logical zero disables the charging current and enables the discharging current into the PB0/AN0 pin, if the ISEN bit is also set. ATD1:ATD2 The ATD1:ATD2 enable bits select one of the four operating modes used for making A/D conversions via the single-slope method. These four modes are given in Table 8-3. These bits have no effect if the ISEN enable bit is cleared. These bits are cleared by a reset of the device and thereby return the analog subsystem to the manual A/D conversion method.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem General Release Specification 111
NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog Subsystem REQUIRED
Table 8-3. A/D Conversion Options
A/D Option Mode Charge Control Current Source and Discharge Disabled A/D Options Current Flow To/From PB0/AN0 ISEN ATD2 ATD1 CHG
Disabled
0
X
X
X
Current control disabled, no source or sink current
1
0
0
0
AGREEMENT
0
Manual Charge and Discharge
Begin sinking current when the CHG bit is cleared and continue to sink current until the CHG bit is set. Begin sourcing current when the CHG bit is set and continue to source current until the CHG bit is cleared. Begin sinking current when the CHG bit is cleared and continue to sink current until the CHG bit is set. (The CHG bit is cleared by writing a logical zero to it or when the CPF2 flag bit is set.) Begin sourcing current when the CHG bit is set; and continue to source current until the CHG bit is cleared. (The CHG bit is set by writing a logical one to it or cleared when the CPF2 flag bit is set.) The CHG bit remains cleared until the next timer TOF occurs. The CHG bit remains set until the next timer ICF occurs. The CHG bit remains cleared until the next timer OCF occurs. The CHG bit remains set until the next timer ICF occurs.
1
0
0
1
1 1 Manual Charge and Automatic Discharge 1
0
1
0
0
1
1
NON-DISCLOSURE
2
Automatic Charge and Discharge (TOF-ICF) Synchronized to Timer Automatic Charge and Discharge (OCF-ICF) Synchronized to Timer
1
1
0
0
1
1
0
1
1
1
1
0
3
1
1
1
1
X = Don't Care
General Release Specification 112 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
ICEN This is a read/write bit that enables a voltage comparison to trigger the input capture register of the programmable timer when the CPF2 flag bit is set. Therefore, an A/D conversion could be started by receiving an OCF or TOF from the programmable timer and then terminated when the voltage on the external ramping capacitor reaches the level of the unknown voltage. The time of termination will be stored in the 16-bit buffer located at $0014 and $0015. This bit is automatically set whenever mode 2 or mode 3 is selected by setting the ATD2 control bit. This bit is cleared by a reset of the device. 1 = Connects the CPF2 flag bit to the timer input capture register 0 = Connects the PB3/AN3 pin to the timer input capture register
NOTE:
For the input capture to occur when the output of comparator 2 goes high, the IEDG bit in the TCR must also be set. When the ICEN bit is set, the input capture function of the programmable timer is not connected to the PB3/AN3/TCAP pin but is driven by the CPF2 output flag from comparator 2. To return to capturing times from external events, the ICEN bit must first be cleared before the timed event occurs. CPIE This is a read/write bit that enables an analog interrupt when either of the CPF1 or CPF2 flag bits is set to a logical one. This bit is cleared by a reset of the device. 1 = Enables analog interrupts when comparator flag bits are set 0 = Disables analog interrupts when comparator flag bits are set
NOTE:
If both the ICEN and CPIE bits are set, they will both generate an interrupt by different paths. One will be the programmable timer interrupt due to the input capture; and the other will be the analog interrupt due to the output of comparator 2 going high. In this case, the input capture interrupt will be entered first due to its higher priority. The analog interrupt will then need to be serviced even if the comparator 2 output has been reset or the input capture flag (ICF) has been cleared.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 113
NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog Subsystem REQUIRED
CP2EN The CP2EN enable bit controls power to voltage comparator 2 in the analog subsystem. Powering down a comparator will drop the supply current by about 100 A. This bit is cleared by a reset of the device. 1 = Writing a logical one powers up voltage comparator 2. 0 = Writing a logical zero powers down voltage comparator 2.
NOTE:
AGREEMENT
Voltage comparators power up slower than digital logic; and their outputs may go through indeterminate states which might set their respective flags (CPF1, CPF2). It is therefore recommended to power up the charge current source first (ISEN); then to power up any comparators, and finally clear the flag bits by writing a logic one to the respective CPFR1 or CPFR2 bits in the ACR. CP1EN The CP1EN enable bit will power down the voltage comparator 1 in the analog subsystem. Powering down a comparator will drop the supply current by about 100 A. This bit is cleared by a reset of the device. 1 = Writing a logical one powers up voltage comparator 1. 0 = Writing a logical zero powers down voltage comparator 1. ISEN The ISEN enable bit will power down the charge current source and disable the discharge device in the analog subsystem. Powering down the current source will drop the supply current by about 200 A. This bit is cleared by a reset of the device. 1 = Writing a logical one powers up the ramping current source and enables the discharge device on the PB0/AN0 pin. 0 = Writing a logical zero powers down the ramping current source and disables the discharge device on the PB0/AN0 pin.
NON-DISCLOSURE
NOTE:
The analog subsystem has support circuitry which draws about 80 A of current. This current will be powered down if both comparators and the charge current source are powered down (ISEN, CP1EN, and CP2EN all cleared). Powering up either comparator or the charge current source will activate the support circuitry.
General Release Specification 114 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
8.5 Analog Status Register
The analog status register (ASR) contains status and control of the comparator flag bits. These bits in the ASR are shown in Figure 8-6. All the bits in this register are cleared by a reset of the device.
$001E Read: Write: Reset: 0 0 Bit 7 CPF2 6 CPF1 5 0 CPFR2 0 4 0 CPFR1 0 3 COE1 0 R 2 VOFF 0 = Reserved 1 CMP2 Bit 0 CMP1 R 0 0
= Unimplemented
Figure 8-6. Analog Status Register (ASR) CPF2 This read-only flag bit is edge sensitive to the rising output of comparator 2. It is set when the voltage on the PB0/AN0 pin rises above the voltage on the sample capacitor which creates a positive edge on the output of comparator 2, regardless of the state of the INV bit in the AMUX register. This bit is reset by writing a logical one to the CPFR2 reset bit in the ASR. This bit is cleared by a reset of the device. 1 = A positive transition on the output of comparator 2 has occurred since the last time the CPF2 flag has been cleared. 0 = A positive transition on the output of comparator 2 has not occurred since the last time the CPF2 flag has been cleared. CPF1 This read-only flag bit is edge sensitive to the rising output of comparator 1. It is set when the voltage on the PB2/AN2 pin rises above the voltage on the PN3/AN3/TCAP pin which creates a positive edge on the output of comparator 1, regardless of the state of the INV bit in the AMUX register. This bit is reset by writing a logical one to the CPFR1 reset bit in the ASR. This bit is cleared by a reset of the device. 1 = A positive transition on the output of comparator 1 has occurred since the last time the CPF1 flag has been cleared. 0 = A positive transition on the output of comparator 1 has not occurred since the last time the CPF1 flag has been cleared.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem General Release Specification 115
NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog Subsystem REQUIRED
CPFR2 Writing a logical one to this write-only flag clears the CPF2 flag in the ASR. Writing a logical zero to this bit has no effect. Reading the CPFR2 bit will return a logical zero. By default, this bit looks cleared following a reset of the device. 1 = Clears the CPF2 flag bit 0 = No effect CPFR1
AGREEMENT
Writing a logical one to this write-only flag clears the CPF1 flag in the ASR. Writing a logical zero to this bit has no effect. Reading the CPFR1 bit will return a logical zero. By default, this bit looks cleared after a reset of the device. 1 = Clears the CPF1 flag bit 0 = No effect
NOTE:
The CPFR1 and CPFR2 bits should be written with logical ones following a power up of either comparator. This will clear out any latched CPF1 or CPF2 flag bits which might have been set during the slower power up sequence of the analog circuitry. If both inputs to a comparator are above the maximum common-mode input voltage (VDD-1.5 V) the output of the comparator is indeterminate and may set the comparator flag. Applying a reset to the device may only temporarily clear this flag as long as both inputs of a comparator remain above the maximum common-mode input voltages. VOFF This read-write bit controls the addition of an offset voltage to the bottom of the sample capacitor. It is not active unless selected by a mask option. Any reads of the VOFF bit location return a logical zero if the analog options' mask option is disabled. During the time that the sample capacitor is connected to an input (either HOLD or DHOLD set), the bottom of the sample capacitor is connected to VSS. The VOFF bit is cleared by a reset of the device. 1 = Enable approximately 100-mV offset to be added to the sample voltage when both the HOLD and DHOLD control bits are cleared. 0 = Connect the bottom of the sample capacitor to VSS.
NON-DISCLOSURE
General Release Specification 116 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
COE1 This read-write bit controls the output of comparator 1 to the PB4 pin. It is not active unless enabled by mask option. Any reads of the COE1 bit location return a logical zero if the analog options mask option is not selected. The COE1 bit is cleared by a reset of the device. 1 = Enables the output of comparator 1 to be ORed with the PB4 data bit and OLVL bit, if the DDRB4 bit is also set 0 = Disables the output of comparator 1 from affecting the PB4 pin CMP2 This read-only bit shows the state of comparator 2 during the time that the bit is read. This bit is, therefore, the current state of the comparator without any latched history. The CMP2 bit will be high if the voltage on the PB0/AN0 pin is greater than the voltage on the PB1/AN1 pin, regardless of the state of the INV bit in the AMUX register. Since a reset disables comparator 2, this bit returns a logical zero following a reset of the device. 1 = Voltage on the positive input on comparator 2 higher than the voltage on the negative input of comparator 2 0 = Voltage on the positive input on comparator 2 lower than the voltage on the negative input of comparator 2 CMP1 This read-only bit shows the state of comparator 1 during the time that the bit is read. This bit is, therefore, the current state of the comparator without any latched history. The CMP1 bit will be high if the voltage on the PB2/AN2 pin is greater than the voltage on the PB3/AN3/TCAP pin, regardless of the state of the INV bit in the AMUX register. Since a reset disables comparator 1, this bit returns a logical zero following a reset of the device. 1 = Voltage on the positive input on comparator 1 higher than the voltage on the negative input of comparator 1 0 = Voltage on the positive input on comparator 1 lower than the voltage on the negative input of comparator 1
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 117
NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog Subsystem REQUIRED 8.6 A/D Conversion Methods
The control bits in the ACR provide various options to charge or discharge current through the PB0/AN0 pin in order to perform singleslope A/D conversions using an external capacitor from the PB0/AN0 pin to VSS as shown in Figure 8-7. The various A/D conversion triggering options are given in Table 8-3.
AGREEMENT
Charge Time =
C x VX I
VDD -1.5 Vdc
UNKNOWN VOLTAGE ON (-) INPUT VOLTAGE ON CAPACITOR CONNECTED TO (+) INPUT CHARGE TIME TO MATCH UNKNOWN MAXIMUM CHARGE TIME TO VDD -1.5 Vdc +5V PB4/AN4 UNKNOWN OR REFERENCE SIGNALS PB3/AN3 PB2/AN2 PB1/AN1 RAMP CAP PB0/AN0 VSS MC68HC05JJ6 MC68HC05JP6 VDD
DISCHARGE TIME TO RESET CAPACITOR
NON-DISCLOSURE
Figure 8-7. Single-Slope A/D Conversion Method The top three bits of the ACR control the charging and discharging current into or out of the PB0/AN0 pin. These three bits will have no effect on the PB0/AN0 pin if the ISEN enable bit is cleared. Any clearing of the ISEN bit will immediately disable both the charge current source and the discharge device. Since all these bits and the ISEN bit are
General Release Specification 118 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
cleared when the device is reset, the MC68HC05JJ6/MC68HC05JP6 starts with the charge and discharge function disabled. The length of time required to reach the maximum voltage to be measured and the speed of the time counting mechanism will determine the resolution of the reading. The time to ramp the external capacitor voltage to match the maximum voltage is dependent on: * * * * * Charging current to external capacitor Value of the external capacitor Clock rate for timing function Any prescaling of the clock to the timing function Desired resolution
The charging behavior is described by the general equation: tCHG = CEXT x VX / ICHG Where: tCHG CEXT VX ICHG = Charge time (seconds) = Capacitance (F) = Unknown voltage (volts) = Charge current (A)
Since the MCU can measure time in a variety of ways, the resolution of the conversion will depend on the length of the time-keeping function and its prescaling to the oscillator frequency (fOSC). Therefore, the charge time also equals: tCHG = P x N / fOSC Where: P = Prescaler value (/ 2, / 4, / 8, etc.) N = Number of counts during charge time fOSC = Oscillator clock frequency (Hz)
NOTE:
Noise on the system ground or the external ramping capacitor can cause the comparator to trip prematurely. Therefore, in any given application it is best to use the fastest possible ramp rate (shortest charge time).
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 119
NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog Subsystem REQUIRED
The above two equations for the charge time, tCHG, can be combined to form this expression for the full scale count (NFS) of the measured time versus the full scale unknown voltage (VFS): NFS = CEXT x VFS x fOSC / (P x ICHG) Since a given timing method has a fixed charge current and prescaler, then the variation in the resultant count for a given unknown voltage is mainly dependent on the operating frequency and the capacitance value used. The desired external capacitance for a given voltage range, fOSC, conversion method, and resolution is defined as: CEXT = NFS x P x ICHG / (VFS x fOSC)
AGREEMENT
NOTE:
The value of any capacitor connected directly to the PB0/AN0 pin should be limited to less than 2 microfarads. Larger capacitances will create high discharge currents which may damage the device or create signal noise. The desired type of capacitor for the ramp capacitor is any of the "poly" film types which have both low leakage and low dielectric absorption (somtimes referred to as memory behavior). Low-cost monolithic ceramics are good for bypass use, but have high dielectric absorption which makes them less desirable for an integration or storage application. Tantalum or aluminum electrolytics have high dielectric absorption and too much leakage, as well. For integration or storage capacitors use capacitors which have a dielectric absorption of less than 0.01%. The full scale voltage range for a given capacitance, fOSC, conversion method, and resolution is defined as: VFS = NFS x P x ICHG / (CEXT x fOSC) Once charged to a given voltage, a finite amount of time will be required to discharge the capacitor back to its start voltage at VSS. This discharge time will be solely based on the value of capacitance used and the sinking current of the internal discharge device. To allow a reasonable time for the capacitor to return to VSS levels, the discharge time should last about 10 milliseconds per microfarad of capacitance attached to the PB0 pin. If the total charge/discharge cycle time is critical, then the discharge time should be at least 1/10 of the most recent charge time.
NOTE:
NON-DISCLOSURE
General Release Specification 120 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
Shorter discharge times may be used if lesser accuracy in the voltage measurement is acceptable.
NOTE:
Sufficient time should be allowed to discharge the external capacitor or subsequent charge times will be shortened with resultant errors in timing conversion. Table 8-4 gives the range of values of each parameter in the A/D timing conversion; and Table 8-5 gives some A/D conversion examples for several bit resolutions. The mode selection bits in the ACR allow four methods of single-slope A/D conversion. Each of these methods is shown in the following figures using the signal names and parameters given in Table 8-4. * * * * Manual start and stop (mode 0) Figure 8-8 Manual start and automatic discharge (mode 1) Figure 8-9 Automatic start and stop from TOF to ICF (mode 2) Figure 8-10 Automatic start and stop from OCF to ICF (mode 3) Figure 8-11
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 121
NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog Subsystem REQUIRED
Table 8-4. A/D Conversion Parameters
Name VX VCAP VMAX ICHG Function Unknown voltage on channel selection bus Charging voltage on external capacitor Maximum charging voltage on external capacitor Charging current on external ramping capacitor VDD = 3 Vdc VDD = 5 Vdc Min VSS VSS -- Typ -- -- -- Max VDD -1.5 VDD -1.5 VDD -1.5 Units V V v A
Refer to 13.10 Analog Subsystem Characteristics (5.0 Vdc) and 13.11 Analog Subsystem Characteristics (3.0 Vdc) Refer to 13.10 Analog Subsystem Characteristics (5.0 Vdc) and 13.11 Analog Subsystem Characteristics (3.0 Vdc)
AGREEMENT
IDIS
Discharge current on external ramping capacitor
mA
tCHG
Time to charge external capacitor (100 kHz < fOSC < 4.0 MHz) 4-bit result 6-bit result 8-bit result 10-bit result 12-bit result Time to discharge external capacitor, CEXT Capacitance of external ramping capacitor Number of counts for ICHG to charge CEXT to VX Prescaler into timing function (/ P) Using core timer Using 16-bit programmable timer Using software loops Clock source frequency (excluding any prescaling)
0.032 0.128 0.512 2.048 8.192 -- 0.0001 1 8 8 24
0.128 0.512 2.048 8.196 32.768 5 0.1 1024 8 8 user defined
2.56 10.24 40.96 120(1) 120(1) 10 2.0(2) 65536 8 8 user defined
ms ms ms ms ms ms/F F counts /P
tDIS CEXT N
NON-DISCLOSURE
P
fOSC
Refer to 13.12 Control Timing (5.0 Vdc) and 13.13 Control Timing (3.0 Vdc)
MHz
1. Limited by requirement for CEXT to be less than 2.0 F. 2. The desired type of capacitor for the ramp capacitor is any of the "poly" film types which have both low leakage and low dielectric absorption (somtimes referred to as memory behavior). Low-cost monolithic ceramics are good for bypass use, but have high dielectric absorption which makes them less desirable for an integration or storage application. Tantalum or aluminum electrolytics have high dielectric absorption and too much leakage, as well. For integration or storage capacitors use capacitors which have a dielectric absorption of less than 0.01%.
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MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
Table 8-5. Sample Conversion Timing (VDD = 5.0 Vdc)
Bits Counts VX (Vdc) A/D Method Software Loop (12 bus cycles) (24 fOSC cycles) Mode 0 or 1 (manual) Programmable Timer (prescaler = 8) Mode 2 or 3 (TOF->ICF or OCF->ICF) Software Loop (12 bus cycles) (24 fOSC cycles) Mode 0 or 1 (manual) Programmable Timer (prescaler = 8) Mode 2 or 3 (TOF->ICF or OCF->ICF) Software Loop (12 bus cycles) (24 fOSC cycles) Mode 0 or 1 (manual) Programmable Timer (prescaler = 8) Mode 2 or 3 (TOF->ICF or OCF->ICF) Programmable Timer (prescaler = 8) Mode 2 or 3 (TOF->ICF or OCF->ICF) Programmable Timer (prescaler = 8) Mode 2 or 3 (TOF->ICF or OCF->ICF) Clock Source Low-Power Oscillator External Pin Oscillator Low-Power Oscillator External Pin Oscillator Low-Power Oscillator External Pin Oscillator Low-Power Oscillator External Pin Oscillator Low-Power Oscillator External Pin Oscillator Low-Power Oscillator External Pin Oscillator Low-Power Oscillator External Pin Oscillator Low-Power Oscillator External Pin Oscillator fOSC (MHz) 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 0.1 1.0 2.0 4.0 tCHG (ms) 3.840 0.384 0.192 0.096 1.280 0.128 0.064 0.032 15.36 1.536 0.768 0.384 5.120 0.512 0.256 0.128 61.44 6.144 3.072 1.536 20.48 2.048 1.024 0.512 (note 1) 8.192 4.096 2.048 (note 1) 32.768 16.384 8.192 CEXT (F) 0.110 0.011 0.006 0.003 0.037 0.004 0.002 0.001 0.439 0.044 0.022 0.011 0.585 0.059 0.029 0.015 1.755 0.176 0.088 0.044 0.585 0.059 0.029 0.015 (note 1) 0.234 0.117 0.059 (note 1) 0.936 0.468 0.234
4
16
3.5
4
16
3.5
6
64
3.5
6
64
3.5
8
256
3.5
8
256
3.5
10
1024
3.5
12
4096
3.5
1. Not usable because the value of CEXT would be greater than 2.0 F
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 123
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tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG x ICHG CEXT tMAX tDIS (MIN) VMAX
AGREEMENT
CHG
COMP2
TOF
OCF
ICF
0
1
2
3
4
5
1
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Point 0 1 2 3 4 5
Action Begin initial discharge and select mode 0 by clearing the CHG, ATD2, and ATD1 control bits in the ACR VCAP falls to VSS. Stop discharge and begin charge by setting CHG control bit in ACR. VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2. VCAP reaches VMAX. Begin next discharge by clearing the CHG control bit in the ACR. Reset CPF2 by writing a 1 to CPFR2.
Software/Hardware Action Software write Wait out minimum tDIS time Software write Wait out tCHG time None Software write
Dependent Variable(s) Software VMAX, IDIS, CEXT Software VX, ICHG, CEXT VMAX, ICHG, CEXT Software
Figure 8-8. A/D Conversion -- Full Manual Control (Mode 0)
General Release Specification 124 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG x ICHG CEXT tDIS (MIN) VMAX
CHG
COMP2
TOF
OCF
ICF
0
1
2
3
1
2
Point 0 1 2
Action
Software/Hardware Action
Dependent Variable(s) Software VMAX, IDIS, CEXT Software
Begin initial discharge and select mode 1 by clearing CHG and Software write ATD2 and setting ATD1 in the ACR VCAP falls to VSS. Stop discharge and begin charge by setting CHG control bit in ACR. VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2, which clears CHG control bit in the ACR. Reset CPF2 by writing a 1 to CPFR2. Wait out minimum tDIS time Software write
3
Wait out tCHG time CPF2 clears CHG control bit
VX, ICHG, CEXT
Figure 8-9. A/D Conversion -- Manual/Auto Discharge Control (Mode 1)
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 125
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tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG x ICHG CEXT tDIS (MIN) VMAX
AGREEMENT
CHG
COMP2 (TCAP) TOF
OCF
ICF
NON-DISCLOSURE
0
1
2
3
1
2
Point
Action Begin initial discharge and select mode 2 by clearing CHG and ATD1 and setting ATD2 in the ACR. Also set ICEN bit in ACR and IEDG bit in TCR. VCAP falls to VSS. Stop discharge and begin charge when the next TOF sets the CHG control bit in ACR. VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2, which causes an ICF from the timer and clears the CHG control bit in ACR. Must clear CPF2 to trap next CPF2 flag.
Software/Hardware Action
Dependent Variable(s)
0
Software write
Software
1 2
Wait out minimum tDIS time. Timer TOF sets the CHG control bit in the ACR.
VMAX, IDIS, CEXT Free-running timer counter overflow, fOSC
3
Wait out tCHG time. Timer ICF clears the CHG control bit in the ACR.
VX, ICHG, CEXT
Figure 8-10. A/D Conversion -- TOF/ICF Control (Mode 2)
General Release Specification 126 Analog Subsystem MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG x ICHG CEXT tDIS (MIN) VMAX
CHG
COMP2 (TCAP) TOF
OCF
ICF
0
1
2
3
1
2
Point 0
Action Begin initial discharge and select mode 3 by clearing CHG and setting ATD2 and ATD1 in the ACR. Also set ICEN bit in ACR and IEDG bit in TCR. VCAP falls to VSS. Set timer output compare registers (OCRH and OCRL) to desired charge start time. Stop discharge and begin charge when the next OCF sets the CHG control bit in ACR. VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2, which causes an ICF from the timer and clears the CHG control bit in ACR. Must clear CPF2 to trap next CPF2 flag. Load next OCF.
Software/Hardware Action Software write
Dependent Variable(s) Software
1
Wait out minimum tDIS time. Software write to OCRH, OCRL Timer OCF sets the CHG control bit in the ACR.
VMAX, IDIS, CEXT, software Free-running timer output compare, fOSC
2
3
Wait out tCHG time. Timer ICF clears the CHG control bit in the ACR.
VX, ICHG, CEXT
Figure 8-11. A/D Conversion -- OCF/ICF Control (Mode 3)
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem General Release Specification 127
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Analog Subsystem REQUIRED 8.7 Voltage Measurement Methods
The methods for obtaining a voltage measurement can use software techniques to express these voltages as absolute or ratiometric readings. In most applications, the external capacitor, the clock source, the reference voltage and the charging current may vary between devices and with changes in supply voltage or ambient temperature. All of these variations must be considered when determining the desired resolution of the measurement. The maximum and minimum extremes for the full scale count will be: NFSMIN = CEXTMIN x VFSMIN x fOSCMIN / (P x ICHGMAX) NFSMAX = CEXTMAX x VFSMAX x fOSCMAX / (P x ICHGMIN) The minimum count should be the desired resolution; and the counting mechanism must be capable of counting to the maximum. The final scaling of the count will be by a math routine which calculates: VX = VREF x (NX - NOFF) / (NREF - NOFF) Where: VREF VX NX NREF NOFF = Known reference voltage = Unknown voltage between VSS and VREF = Conversion count for unknown voltage = Conversion count for known reference voltage (VREF) = Conversion count for minimum reference voltage (VSS)
NON-DISCLOSURE
AGREEMENT
When VREF is a stable voltage source, such as a zener or other reference source, then the unknown voltage will be determined as an absolute reading. If VREF is the supply source to the device (VDD), then the unknown voltage will be determined as a ratio of VDD or a ratiometric reading. If the unknown voltage applied to the comparator is greater than its common-mode range (VDD -1.5 volts), then the external capacitor will try to charge to the same level. This will cause both comparator inputs to be above the common-mode range and the output of the comparator will be indeterminate. In this case, the comparator output flags may also
General Release Specification 128 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
be set even if the actual voltage on the positive input (+) is less than the voltage on the negative input (-). All A/D conversion methods should have a maximum time check to determine if this case is occurring. Once the maximum timeout detection has been made, the state of the comparator outputs can be tested to determine the situation. However, such tests should be carefully designed when using modes 1, 2, or 3, as these modes cause the immediate automatic discharge of the external ramping capacitor before any software check can be made of the output state of comparator 2.
NOTE:
All A/D conversion methods should include a test for a maximum elapsed time to detect error cases where the inputs may be outside of the design specification.
8.7.1 Absolute Voltage Readings The absolute value of a voltage measurement can be calculated in software by first taking a reference reading from a fixed source and then comparing subsequent unknown voltages to that reading as a percentage of the reference voltage multiplied times the known reference value. The accuracy of absolute readings will depend on the error sources taken into account using the features of the analog subsystem and appropriate software as described in Table 8-6. As can be seen from this table, most of the errors can be reduced by frequent comparisons to a known voltage, use of the inverted comparator inputs, and averaging of multiple samples. 8.7.1.1 Internal Absolute Reference If a stable source of VDD is provided, the reference measurement point can be internally selected. In this case, the reference reading can be taken by setting the VREF bit and clearing the MUX1:MUX4 bits in the AMUX register. This connects the channel selection bus to the VDD pin. To stay within the VMAX range, the DHOLD bit should be used to select the 1/2 divided input.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 129
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8.7.1.2 External Absolute Reference If a stable external source is provided, the reference measurement point can be any one of the channel selected pins from PB1 through PB4. In this case, the reference reading can be taken by setting the MUX bit in the AMUX which connects channel selection bus to the pin connected to the external reference source. If the external reference is greater than VDD -1.5 volts, then the DHOLD bit should be used to select the 1/2 divided input. Table 8-6. Absolute Voltage Reading Errors
Error Source Change in reference voltage Change in magnitude of ramp current source Non-linearity of ramp current source vs. voltage Change in magnitude of ramp capacitor Frequency shift in internal low-power oscillator Frequency shift in external oscillator Sampling capacitor leakage Internal voltage divider ratio Input offset voltage of comparator 2 Noise internal to MCU Accuracy Improvements Possible In Hardware Provide closer tolerance reference Not adjustable In Software Calibration and storage of reference source over temperature and supply voltage Compare unknown with recent measurement from reference Calibration and storage of voltages at 1/4, 1/2, 3/4, and FS Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference OR avoid use of divided input Sum two readings on reference or unknown using INV and INV control bit and divide by 2 (average of both) Average multiple readings on both the reference and the unknown voltage Average multiple readings on both the reference and the unknown voltage
AGREEMENT
Not adjustable
Provide closer tolerance ramp capacitor
NON-DISCLOSURE
Use external oscillator with crystal
Provide closer tolerance crystal Use faster conversion times
Not adjustable
Not adjustable Close decoupling at VDD and VSS pins and reduce supply source impedance Close decoupling of power supply, low source impedances, good board layout, use of multi-layer board
Noise external to MCU
General Release Specification 130 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
8.7.2 Ratiometric Voltage Readings The ratiometric value of a voltage measurement can be calculated in software by first taking a reference reading from a reference source and then comparing subsequent unknown voltages to that reading as a percentage of the reference value. The accuracy of ratiometric readings will depend on the variety of sources, but will generally be better than for absolute readings. Many of these error sources can be taken into account using the features of the analog subsystem and appropriate software as described in Table 8-7. As with absolute measurements, most of the errors can be reduced by frequent comparisons to the reference voltage, use of the inverted comparator inputs, and averaging of multiple samples. 8.7.2.1 Internal Ratiometric Reference If readings are to be ratiometric to VDD, the reference measurement point can be internally selected. In this case, the reference reading can be taken by setting the VREF bit and clearing the MUX1:MUX4 bits in the AMUX register, which connects the channel selection bus to the VDD pin. To stay within the VMAX range, the DHOLD bit should be used to select the 1/2 divided input. 8.7.2.2 External Ratiometric Reference If readings are to be ratiometric to some external source, the reference measurement point can be connected to any one of the channel selected pins from PB1 through PB4. In this case, the reference reading can be taken by setting the MUX bit in the AMUX, which connects channel selection bus to the pin connected to the external reference source. If the external reference is greater than VDD -1.5 volts, then the DHOLD bit should be used to select the 1/2 divided input.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 131
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Table 8-7. Ratiometric Voltage Reading Errors
Accuracy Improvements Possible Error Source In Hardware Change in reference voltage Change in magnitude of ramp current source Non-linearity of ramp current source vs. voltage Change in magnitude of ramp capacitor Frequency shift in internal low-power oscillator Frequency shift in external oscillator Not required for ratiometric Not adjustable Not adjustable Not required for ratiometric Not required for ratiometric Not required for ratiometric In Software Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Calibration and storage of voltages at 1/4, 1/2, 3/4, and FS Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Sum two readings on reference or unknown using INV and INV control bit and divide by 2 (average of both) Average multiple readings on both the reference and the unknown voltage Average multiple readings on both the reference and the unknown voltage
AGREEMENT NON-DISCLOSURE
Sampling capacitor leakage Use faster conversion times Internal voltage divider ratio Not adjustable Input offset voltage of comparator 2
Not adjustable Close decoupling at VDD and VSS pins and reduce supply source impedance Close decoupling of power supply, low source impedances, good board layout, use of multi-layer board
Noise internal to MCU
Noise external to MCU
General Release Specification 132 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
8.8 Voltage Comparator Features
The two internal comparators can be used as simple voltage comparators if set up as described in Table 8-8. Both comparators can be active in the wait mode and can directly restart the part by means of the analog interrupt. Both comparators can also be active in stop mode, but cannot directly restart the part. However, the comparators can directly drive a PA4 or PA5 pin, which can then be connected externally to activate either a port interrupt on the PA0:PA3 pins or the IRQ pin. Table 8-8. Voltage Comparator Setup Conditions
Comparator Current Source Enable Not Affected ISEN = 0 Discharge Device Disable Not Affected ISEN = 0 Port B Pin as Inputs DDRB2 = 0 DDRB3 = 0 DDRB0 = 0 DDRB1 = 0 Port B Pin Pulldowns Disabled PDIB2 = 1 PDIB3 = 1 PDIB0 = 1 PDIB1 = 1 Prog. Timer Input Capture Source Not Affected ICEN = 0 IEDG = 1
1 2
Voltage Comparator 1 Voltage comparator 1 is always connected to two of the port B I/O pins. These pins should be configured as inputs and have their software programmable pulldowns disabled. Also, the negative input of voltage comparator 1 is connected to the PB3/AN3/TCAP and shared with the input capture function of the 16-bit programmable timer. Therefore, the timer input capture interrupt should be disabled so that changes in the voltage on the PB3/AN3/TCAP pin do not cause unwanted input capture interrupts. The output of comparator 1 can be connected to the port logic driving the PB4/AN4/TCMP/CMP1 pin such that the output of the comparator is ORed with the PB4 data bit and the OLVL bit from the 16-bit timer. This capability requires that the proper mask option and the COE1 bit set in the ASR at location $001E. Voltage Comparator 2 Voltage comparator 2 can be used as a simple comparator if its charge current source and discharge device are disabled by clearing the ISEN bit in the ACR. If the ISEN bit is set, the internal ramp discharge device connected to PB0/AN0 may become active and try
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem General Release Specification 133
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to pull down any voltage source that may be connected to that pin. Also, since voltage comparator 2 is always connected to two of the port B I/O pins, these pins should be configured as inputs and have their software programmable pulldowns disabled.
8.9 Current Source Features
The internal current source connected to the PB0/AN0 pin supplies about 100 A of current when the discharge device is disabled and the current source is active. Therefore, this current source can be used in an application if the ISEN enable bit is set to power up the current source and by setting the A/D conversion method to manual mode 0 (ATD1 and ATD2 cleared) and the charge current is enabled (CHG set).
AGREEMENT
8.10 Internal Temperature Sensing Diode Features
An internal diode is forward biased to VSS and will have its voltage change approximately 2 mV for each degree Centigrade rise in the temperature of the device. This temperature-sensing diode is powered up from a current source only during the time that the diode is selected. When on, this current source adds about 30 A to the IDD current. The temperature-sensing diode can be selected by setting both the HOLD and DHOLD bits in the AMUX register (see 8.3 Analog Multiplex Register).
NON-DISCLOSURE
8.11 Sample and Hold
When using the internal sample capacitor to capture a voltage for later conversion, the HOLD or DHOLD bit must be cleared first before changing any channel selection. If both the HOLD (or DHOLD) bit and the channel selection are changed on the same write cycle, the sample may be corrupted during the switching transitions.
General Release Specification 134 Analog Subsystem
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Analog Subsystem
NOTE:
The sample capacitor can be affected by excessive noise created with respect to the device's VSS pin such that it may appear to leak down or charge up depending on the voltage level stored on the sample capacitor. It is recommended to avoid switching large currents through the port pins while a voltage is to remain stored on the sample capacitor. The additional option of adding an offset voltage to the bottom of the sample capacitor allows unknown voltages near VSS to be sampled and then shifted up past the comparator offset and the device offset caused by a single VSS return pin. This offset also provides a means to measure the internal VSS level, regardless of the comparator offset, to determine NOFF as described in 8.7 Voltage Measurement Methods. In either case, the proper mask option must be selected and the VOFF bit must be set in the ASR. It is not necessary to switch the VOFF bit during conversions, since the offset is controlled by the HOLD and DHOLD bits when the VOFF is active. Refer to 8.3 Analog Multiplex Register for more details on the design and decoding of the sample and hold circuit.
8.12 Port B Interaction with Analog Inputs
The analog subsystem is connected directly to the port B I/O pins without any intervening gates. It is, therefore, possible to measure the voltages on port B pins set as inputs or to have the analog voltage measurements corrupted by port B pins set as outputs.
8.13 Port B Pins as Inputs
All the port B pins will power up as inputs or return to inputs after a reset of the device, since the bits in the port B data direction register will be reset. If any port B pins are to be used for analog voltage measurements, they should be left as inputs. In this case, not only can the voltage on the pin be measured, but the logic state of the port B pins can be read from location $0002.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Analog Subsystem
General Release Specification 135
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Analog Subsystem REQUIRED 8.14 Port B Pulldowns
All the port B pins have internal software programmable pulldown devices available dependent on the software pulldown inhibit mask option. If the pulldowns are enabled, they will create an approximate 100-A load to any analog source connected to the pin. In some cases, the analog source may be able to supply this current without causing any error due to the analog source output impedance. Since this may not always be true, it is therefore best to disable port B pulldowns on those pins used for analog input sources.
AGREEMENT
8.15 Noise Sensitivity
In addition to the normal effects of electrical noise on the analog input signal, there can also be other noise-related effects caused by the digital-to-analog interface. Since there is only one VSS return for both the digital and the analog subsystems on the device, currents in the digital section may affect the analog ground reference within the device. This can add voltage offsets to measured inputs or cause channel-to-channel crosstalk. To reduce the impact of these effects, there should be no switching of heavy I/O currents to or from the device while there is a critical analog conversion or voltage comparison in process. Limiting switched I/O currents to 2 to 4 mA during these times is recommended. A noise reduction benefit can be gained with 0.1 F bypass capacitors from each analog input (PB4:PB1) to the VSS pin. Also, try to keep all the digital power supply or load currents from passing through any conductors which are the return paths for an analog signal.
NON-DISCLOSURE
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MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 9. Simple Serial Interface
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . .140 9.3.3 Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . .140 9.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9.2 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to provide efficient serial communications with peripheral devices or other MCUs. SIOP is implemented as a 3-wire master/slave system with serial clock (SCK), serial data input (SDI), and serial data output (SDO). A block diagram of the SIOP is shown in Figure 9-1. The SIOP subsystem shares its input/output pins with port B. When the SIOP is enabled (SPE bit set in the SCR), the port B data direction and data registers are bypassed by the SIOP. The port B data direction and data registers will remain accessible and can be altered by the application software, but these actions will not affect the SIOP transmitted or received data.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Simple Serial Interface
General Release Specification 137
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PORTB LOGIC OSCILLATOR CLOCK /2 SPR0 SPR1 SIOP CONTROL REGISTER (SCR) CPHA PORTB LOGIC MSTR SPE LSBF SPIR PB6 SDI PORTB LOGIC $000A SIOP INTERRUPT SPIF SIOP STATUS REGISTER (SSR) DCOL D0 D1 D2 D3 D4 D5 D6 D7 LATCH Q S R DIN CLK COMP ERROR DOUT 8-BIT SHIFT REGISTER PB5 SDO CLOCK DIVIDER AND SELECT CLOCK CONTROL PB7 SCK
AGREEMENT
SPIE
INTERNAL HC05 BUS
FORMAT CONTROL LSB OR MSB FIRST
$000B
NON-DISCLOSURE
$000C INTERNAL HC05 BUS
Figure 9-1. SIOP Block Diagram
General Release Specification 138 Simple Serial Interface
SDR0 SDR1 SDR2 SDR3 SDR4 SDR5 SDR6 SDR7 SIOP DATA REGISTER (SDR)
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Simple Serial Interface
9.3 SIOP Signal Format
The SIOP subsystem can be software configured for master or slave operation. No external mode selection inputs are available (for instance, no slave select pin).
9.3.1 Serial Clock (SCK) The state of the SCK output remains a fixed logic level during idle periods between data transfers. The edges of SCK indicate the beginning of each output data transfer and latch any incoming data received. The first bit of transmitted data is output from the SDO pin on the first falling edge of SCK. The first bit of received data is accepted at the SDI pin on the first rising edge of SCK after the first falling edge. The transfer is terminated upon the eighth rising edge of SCK. The idle state of the SCK is determined by the state of the CPHA bit in the SCR. When the CPHA is clear, SCK will remain idle at a logical one as shown in Figure 9-2. When the CPHA is set, SCK will remain idle at a logical zero as shown in Figure 9-3. In both cases, the SDO changes data on the falling edge of the SCK, and the SDI latches data in on the rising edge of SCK. The master and slave modes of operation differ only in the means of sourcing the SCK. In master mode, SCK is driven from an internal source within the MCU. In slave mode, SCK is driven from a source external to the MCU. The SCK frequency is based on one of four divisions of the oscillator clock that is selected by the SPR0 and SPR1 bits in the SCR.
BIT 1 SDO BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
SCK (CPHA = 0) 100 ns SDI BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 100 ns
(IDLE = 1)
Figure 9-2. SIOP Timing Diagram (CPHA = 0)
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Simple Serial Interface General Release Specification 139
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BIT 1 SDO
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
SCK (CPHA = 1)
(IDLE = 0) 100 ns 100 ns
SDI BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
Figure 9-3. SIOP Timing Diagram (CPHA = 1)
AGREEMENT
9.3.2 Serial Data Input (SDI) The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New data is presented to the SDI pin on the falling edge of SCK. Valid data must be present at least 100 nanoseconds before the rising edge of SCK and remain valid for 100 nanoseconds after the rising edge of SCK. See Figure 9-3.
9.3.3 Serial Data Output (SDO) The SDO pin becomes an output as soon as the SIOP subsystem is enabled. The state of the PB5/SDO pin reflects the value of the first bit received on the previous transmission. Prior to enabling the SIOP, the PB5/SDO can be initialized to determine the beginning state. While SIOP is enabled, the port B logic cannot be used as a standard output since that pin is connected to the last stage of the SIOP serial shift register. A control bit (LSBF) is included in the SCR to allow the data to be transmitted in either the MSB first format or the LSB first format. The first data bit will be shifted out to the SDO pin on the first falling edge of the SCK. The remaining data bits will be shifted out to the SDI pin on subsequent falling edges of SCK. The SDO pin will present valid data at least 100 nanoseconds before the rising edge of the SCK and remain valid for 100 nanoseconds after the rising edge of SCK. See Figure 9-3.
NON-DISCLOSURE
General Release Specification 140 Simple Serial Interface
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Simple Serial Interface
9.4 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register (SCR) located at address $000A, the SIOP status register (SSR) located at address $000B, and the SIOP data register (SDR) located at address $000C.
9.4.1 SIOP Control Register The SIOP control register (SCR) is located at address $000A and contains seven control bits and a write-only reset of the interrupt flag. Figure 9-4 shows the position of each bit in the register and indicates the value of each bit after reset.
$000A Read: SPIE Write: Reset: 0 0 0 0 SPE LSBF MSTR SPIR 0 0 0 0 Bit 7 6 5 4 3 0 CPHA SPR1 SPR0 2 1 Bit 0
Figure 9-4. SIOP Control Register (SCR) SPIE -- Serial Peripheral Interrupt Enable
NOTE:
If the SPIE bit is cleared just after the serial interrupt sequence has started (for instance, the CPU status is being stacked), then the CPU will be unable to determine the source of the interrupt and will vector to the reset vector as a default.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Simple Serial Interface
General Release Specification 141
NON-DISCLOSURE
The SPIE bit enables the SIOP to generate an interrupt whenever the SPIF flag bit in the SSR is set. Clearing the SPIE bit will not affect the state of the SPIF flag bit and will not terminate a serial interrupt once the interrupt sequence has started. Reset clears the SPIE bit. 1 = Serial interrupt enabled 0 = Serial interrupt disabled
AGREEMENT
REQUIRED
Simple Serial Interface REQUIRED
SPE -- Serial Peripheral Enable The SPE bit switches the port B interface such that SDO/PB5 is the serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a serial clock input in the slave mode or a serial clock output in the master mode. The port B DDR and data registers can be manipulated as usual, but these actions will not affect the transmitted or received data. The SPE bit is readable and writable at any time, but clearing the SPE bit while a transmission is in progress will 1) abort the transmission, 2) reset the serial bit counter, and 3) convert port B to a general-purpose I/O port. Reset clears the SPE bit. 1 = Serial peripheral enabled (port B I/O disabled) 0 = Serial peripheral disabled (port B I/O enabled) LSBF -- Least Significant Bit First The LSBF bit controls the format of the transmitted and received data to be transferred LSB or MSB first. Reset clears this bit. 1 = LSB transferred first 0 = MSB transferred first MSTR -- Master Mode Select The MSTR bit configures the serial I/O port for master mode. A transfer is initiated by writing to the SDR. Also, the SCK pin becomes an output providing a synchronous data clock dependent upon the divider of the oscillator frequency selected by the SPR0:SPR1 bits. When the device is in master mode, the SDO and SDI pins do not change function. These pins behave exactly the same in both the master and slave modes. The MSTR bit is readable and writable at any time regardless of the state of the SPE bit. Clearing the MSTR bit will abort any transfers that may have been in progress. Reset clears the MSTR bit, placing the SIOP subsystem in slave mode. 1 = SIOP set up as master, SCK is an output 0 = SIOP set up as slave, SCK is an input
NON-DISCLOSURE
General Release Specification 142
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Simple Serial Interface Freescale Semiconductor
Simple Serial Interface
SPIR -- Serial Peripheral Interrupt Reset The SPIR bit is a write-only control to reset the SPIF flag bit in the SSR. Reading the SPIR bit will return a logical zero. 1 = Reset the SPIF flag bit 0 = No effect CPHA -- Clock Phase The CPHA bit controls the clock timing and phase in the SIOP. Data is changed on the falling edge of SCK and data is captured (read) on the rising edge of SCK. This bit is cleared by reset. 1 = SCK idle low 0 = SCK idle high SPR0:SPR1 -- Serial Peripheral Clock Rate Selects The SPR0 and SPR1 bits select one of four clock rates given in Table 9-1 to be supplied on the PB7/SCK pin when the device is configured with the SIOP as a master (MSTR = 1). The fastest rate is when both SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits are cleared by reset, which places the SIOP clock selection at the slowest rate. Table 9-1. SIOP Clock Rate Selection
SPR1 0 0 1 1 SPR0 0 1 0 1 SIOP Clock Rate (Oscillator Frequency Divided by:) 64 32 16 8
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Simple Serial Interface
General Release Specification 143
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AGREEMENT
REQUIRED
Simple Serial Interface REQUIRED
9.4.2 SIOP Status Register The SIOP status register (SSR) is located at address $000B and contains two read-only bits. Figure 9-5 shows the position of each bit in the register and indicates the value of each bit after reset.
$000B Read: Write: Bit 7 SPIF 6 DCOL 5 0 4 0 3 0 2 0 1 0 Bit 0 0
AGREEMENT
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-5. SIOP Status Register (SSR) SPIF -- Serial Port Interrupt Flag The SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data transfer has been completed. It has no effect on any future data transfers and can be ignored. The SPIF bit can be cleared by reading the SSR followed by a read or write of the SDR or by writing a logical one to the SPIR bit in the SCR. If the SPIF is cleared before the last rising edge of SCK it will be set again on the last rising edge of SCK. Reset clears the SPIF bit. 1 = Serial transfer complete, serial interrupt if the SPIE bit in SCR is set 0 = Serial transfer in progress or serial interface idle DCOL -- Data Collision The DCOL is a read-only status bit which indicates that an illegal access of the SDR has occurred. The DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF is set. Reading or writing the SDR during this time will result in invalid data being transmitted or received. The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or write of the SDR. If the last part of the clearing sequence is done after another transfer has started, the DCOL bit will be set again. Reset clears the DCOL bit. 1 = Illegal access of the SDR occurred 0 = No illegal access of the SDR detected
NON-DISCLOSURE
General Release Specification 144 Simple Serial Interface
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Simple Serial Interface
9.4.3 SIOP Data Register The SIOP data register (SDR) is located at address $000C and serves as both the transmit and receive data register. Writing to this register will initiate a message transmission if the node is in master mode. The SIOP subsystem is not double buffered and any write to this register will destroy the previous contents. The SDR can be read at any time. However, if a transfer is in progress, the results may be ambiguous. Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted and/or received. Figure 9-6 shows the position of each bit in the register. This register is not affected by reset.
$000C Read: Bit 7 Write: Reset: Unaffected by Reset 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0
Figure 9-6. SIOP Data Register (SDR)
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Simple Serial Interface
General Release Specification 145
NON-DISCLOSURE
AGREEMENT
REQUIRED
Simple Serial Interface REQUIRED NON-DISCLOSURE
General Release Specification 146 Simple Serial Interface
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 10. Core Timer
10.1 Contents
10.2 10.3 10.4 10.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Core Timer Status and Control Register . . . . . . . . . . . . . . . .149 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . .151 COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.2 Introduction
This section describes the operation of the core timer and the COP watchdog as shown by the block diagram in Figure 10-1.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Core Timer
General Release Specification 147
NON-DISCLOSURE
AGREEMENT
REQUIRED
Core Timer REQUIRED
RESET INTERNAL CLOCK OVERFLOW $0009 CORE TIMER COUNTER REGISTER BITS 0-7 OF 15-STAGE RIPPLE COUNTER /4 /2 OSC1
INTERNAL CLOCK / 1024
AGREEMENT
INTERNAL DATA BUS
CORE TIMER INTERRUPT REQUEST
CTOFR
CTOFE
RTIFR
CTOF
RTIE
RTIF
$0008 RESET
CORE TIMER STATUS/CONTROL REGISTER RT1 RTI RATE SELECT $1FF0 COP REGISTER /2 /2 /2 /2 /2 /2 RT0
/2 POWER-ON RESET
NON-DISCLOSURE
COPC
/2
/2
/2
/2
COP WATCHDOG RESET
RESET
Figure 10-1. Core Timer Block Diagram
General Release Specification 148 Core Timer
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Core Timer
10.3 Core Timer Status and Control Register
The read/write core timer status and control register (CTSCR) contains the interrupt flag bits, interrupt enable bits, interrupt flag bit resets, and the rate selects for the real-time interrupt as shown in Figure 10-2.
$0008 Read: Write: Reset: 0 0 0 0 Bit 7 CTOF 6 RTIF CTOFE RTIE CTOFR 0 RTIFR 0 5 4 3 0 2 0 RT1 1 RT0 1 1 Bit 0
= Unimplemented
Figure 10-2. Core Timer Status and Control Register (CTSCR) CTOF -- Core Timer Overflow Flag This read-only flag becomes set when the first eight stages of the core timer counter roll over from $FF to $00. The CTOF flag bit generates a timer overflow interrupt request if CTOFE is also set. The CTOF flag bit is cleared by writing a logic one to the CTOFR bit. Writing to CTOF has no effect. Reset clears CTOF. 1 = Overflow in core timer has occurred. 0 = No overflow of core timer since CTOF last cleared RTIF -- Real-Time Interrupt Flag This read-only flag becomes set when the selected RTI output becomes active. RTIF generates a real-time interrupt request if RTIE is also set. The RTIF enable bit is cleared by writing a logic one to the RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF. 1 = Overflow in real-time counter has occurred. 0 = No overflow of real-time counter since RTIF last cleared CTOFE -- Core Timer Overflow Interrupt Enable This read/write bit enables core timer overflow interrupts. Reset clears CTOFE. 1 = Core timer overflow interrupts enabled 0 = Core timer overflow interrupts disabled
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Core Timer
General Release Specification 149
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AGREEMENT
REQUIRED
Core Timer REQUIRED
RTIE -- Real-Time Interrupt Enable This read/write bit enables real-time interrupts. Reset clears RTIE. 1 = Real-time interrupts enabled 0 = Real-time interrupts disabled CTOFR -- Core Timer Overflow Flag Reset Writing a logic one to this write-only bit clears the CTOF bit. CTOFR always reads as a logic zero. Reset does not affect CTOFR. 1 = Clear CTOF flag bit 0 = No effect on CTOF flag bit RTIFR -- Real-Time Interrupt Flag Reset Writing a logic one to this write-only bit clears the RTIF bit. RTIFR always reads as a logic zero. Reset does not affect RTIFR. 1 = Clear RTIF flag bit 0 = No effect on RTIF flag bit RT1 and RT0 -- Real-Time Interrupt Select Bits 1 and 0 These read/write bits select one of four real-time interrupt rates, as shown in Table 10-1. Because the selected RTI output drives the COP watchdog, changing the real-time interrupt rate also changes the counting rate of the COP watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout period and longest real-time interrupt period.
NON-DISCLOSURE
AGREEMENT
NOTE:
Changing RT1 and RT0 when a COP timeout is imminent or uncertain may cause a real-time interrupt request to be missed or an additional real-time interrupt request to be generated. Clear the COP timer just before changing RT1 and RT0.
General Release Specification 150 Core Timer
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Core Timer
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow Interrupt Period TOF = 1/(fOSC / 211) (microseconds) @ fOSC (MHz) 4.2 MHz 2.0 MHz 1.0 MHz 0 488 1024 2048 0 1 1 0 1 0 1 2
15
RTI Rate RT1 RT0 = fOSC divided by:
Real-Time Interrupt Period (RTI) (milliseconds) @ fOSC (MHz) 4.2 MHz 7.80 15.6 31.2 62.4 2.0 MHz 16.4 32.8 65.5 131 1.0 MHz 32.8 65.5 131 262
COP Timeout Period COP = 7 to 8 RTI Periods (milliseconds) @ fOSC (MHz) 4.2 MHz Min 54.6 109 218 437 Max 62.4 125 250 499 2.0 MHz Min 115 229 459 918 Max 131 262 524 1049 1.0 MHz Min 229 459 918 1835 Max 262 524 1049 2097
216 217 218
10.4 Core Timer Counter Register
A 15-stage ripple counter driven by a divide-by-eight prescaler is the basis of the core timer. The value of the first eight stages is readable at any time from the read-only timer counter register as shown in Figure 10-3.
$0009 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
= Unimplemented
Figure 10-3. Core Timer Counter Register (CTCR) Power-on clears the entire counter chain and begins clocking the counter. After the startup delay (16 or 4064 internal bus cycles depending on a mask option), the power-on reset circuit is released, clearing the counter again and allowing the MCU to come out of reset. Each count of the timer counter register takes eight oscillator cycles or four cycles of the internal bus. A timer overflow function at the eighth counter stage allows a timer interrupt every 2048 oscillator clock cycles or every 1024 internal bus cycles.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Core Timer General Release Specification 151
NON-DISCLOSURE
AGREEMENT
REQUIRED
Core Timer REQUIRED 10.5 COP Watchdog
Four counter stages at the end of the core timer make up the computer operating properly (COP) watchdog which can be enabled by a mask option. The COP watchdog is a software error detection system that automatically times out and resets the MCU if the COP watchdog is not cleared periodically by a program sequence. Writing a logic zero to COPC bit in the COP register clears the COP watchdog and prevents a COP reset.
$1FF0 Read: Write: Reset: = Unimplemented Unaffected by Reset COPC Bit 7 6 5 4 3 2 1 Bit 0
AGREEMENT
Figure 10-4. COP and Security Register (COPR) COPC -- COP Clear This write-only bit resets the COP watchdog. The COP watchdog is active in the run, wait, and halt modes of operation if the COP is enabled by a mask option. The STOP instruction disables the COP watchdog by clearing the counter and turning off its clock source. In applications that depend on the COP watchdog, the STOP instruction can be disabled by the stop mask option. In applications that have wait cycles longer than the COP timeout period, the COP watchdog can be disabled by the stop mask option. Table 10-2 summarizes recommended conditions for enabling and disabling the COP watchdog.
NON-DISCLOSURE
NOTE:
If the voltage on the IRQ pin exceeds 1.5 x VDD, the COP watchdog turns off and remains off until the IRQ pin voltage falls below 1.5 x VDD.
General Release Specification 152 Core Timer
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Core Timer
Table 10-2. COP Watchdog Recommendations
Voltage on IRQ Pin Less than 1.5 x VDD Less than 1.5 x VDD Less than 1.5 x VDD More than 1.5 x VDD Mask Option to Select HALT1 1 1 0 X Wait/Halt Time Less than COP Timeout Period Greater than COP Timeout Period X3 X Recommended COP Watchdog Condition Enabled2 Disabled Disabled Disabled
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Core Timer
General Release Specification 153
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AGREEMENT
NOTES: 1. The HALT mask option converts STOP instructions to HALT instructions. 2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction. 3. X = Don't Care
REQUIRED
Core Timer REQUIRED NON-DISCLOSURE
General Release Specification 154 Core Timer
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 11. Programmable Timer
11.1 Contents
11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Alternate Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .160 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . .164 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Timer Operation during Wait Mode. . . . . . . . . . . . . . . . . . . . .169
11.10 Timer Operation during Stop Mode . . . . . . . . . . . . . . . . . . . .169 11.11 Timer Operation during Halt Mode . . . . . . . . . . . . . . . . . . . . .169
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Programmable Timer
General Release Specification 155
NON-DISCLOSURE
AGREEMENT
REQUIRED
Programmable Timer REQUIRED 11.2 Introduction
The MC68HC05JJ6/MC68HC05JP6 MCU contains a 16-bit programmable timer with an input capture function and an output compare function as shown by the block diagram in Figure 11-1. The basis of the capture/compare timer is a 16-bit free-running counter which increases in count with every four internal bus clock cycles. The counter is the timing reference for the input capture and output compare functions. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. Software can read the value in the 16-bit free-running counter at any time without affecting the counter sequence. The I/O registers for the input capture and output compare functions are pairs of 8-bit registers, because of the 16-bit timer architecture used. Each register pair contains the high and low bytes of that function. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. Because the counter is 16 bits long and preceded by a fixed divide-byfour prescaler, the counter rolls over every 262,144 internal clock cycles (every 524,288 oscillator clock cycles). Timer resolution with a 4-MHz crystal oscillator is 2 microsecond/count. The interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (TCR) located at $0012, and the status of the interrupt flags can be read from the timer status register (TSR) located at $0013.
NON-DISCLOSURE
AGREEMENT
General Release Specification 156 Programmable Timer
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Programmable Timer
PB3 AN3 TCAP
INPUT SELECT MUX
EDGE SELECT & DETECT LOGIC ICF
ICRH ($0014)
ICRL ($0015)
CPF2 FLAG BIT FROM ANALOG SUBSYSTEM
TMRH ($0018) IEDG
TMRL ($0019)
ACRH ($001A)
ACRL ($001B)
ICEN CONTROL BIT OVERFLOW (TOF)
16-BIT COUNTER
/4
16-BIT COMPARATOR DQ OCRH ($0016) OCRL ($0017) C PIN I/O LOGIC PB4 AN4 TCMP
ANALOG COMP 1
RESET OLVL OCIE IEDG TOIE OCF TOF ICIE ICF
TIMER CONTROL REGISTER $0012 INTERNAL DATA BUS
TIMER STATUS REGISTER $0013
Figure 11-1. Programmable Timer Overall Block Diagram
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Programmable Timer
General Release Specification 157
NON-DISCLOSURE
TIMER INTERRUPT REQUEST
AGREEMENT
INTERNAL CLOCK (OSC / 2)
OLVL
OCF
REQUIRED
Programmable Timer REQUIRED 11.3 Timer Registers
The functional block diagram of the 16-bit, free-running timer counter and timer registers is shown in Figure 11-2. The timer registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
LATCH
TMRL ($0019)
READ TMRL
AGREEMENT
READ TMRH RESET
READ ($FFFC)
TMRH ($0018)
TMR LSB /4 INTERNAL CLOCK (OSC / 2) TIMER INTERRUPT REQUEST TOF TIMER STATUS REG. $0013 INTERNAL DATA BUS
16-BIT COUNTER
OVERFLOW (TOF)
TIMER CONTROL REG. $0012
NON-DISCLOSURE
Figure 11-2. Programmable Timer Block Diagram The timer registers (TMRH and TMRL) shown in Figure 11-3 are readonly locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC.
General Release Specification 158 Programmable Timer
TOIE
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Programmable Timer
$0018 Read: Write: Reset:
Bit 7 Bit 15
6 14
5 13
4 12
3 11
2 10
1 9
Bit 0 Bit 8
1
1
1
1
1
1
1
1
$0019 Read: Write: Reset:
Bit 7 Bit 7
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
1
1
1
1
1
1
0
0
= Unimplemented
Figure 11-3. Programmable Timer Registers (TMRH and TMRL) The TMRL latch is a transparent read of the LSB until a read of the TMRH takes place. A read of the TMRH latches the LSB into the TMRL location until the TMRL is again read. The latched value remains fixed even if multiple reads of the TMRH take place before the next read of the TMRL. Therefore, when reading the MSB of the timer at TMRH, the LSB of the timer at TMRL must also be read to complete the read sequence. During power-on reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator startup delay. Because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag bit can only be reset by reading the TMRL after reading the TSR. Other than clearing any possible TOF flags, reading the TMRH and TMRL in any order or any number of times does not have any effect on the 16-bit free-running counter.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Programmable Timer
General Release Specification 159
NON-DISCLOSURE
AGREEMENT
REQUIRED
Programmable Timer REQUIRED
NOTE:
To prevent interrupts from occurring between readings of the TMRH and TMRL, set the I bit in the condition code register (CCR) before reading TMRH and clear the I bit after reading TMRL.
11.4 Alternate Counter Registers
The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in Figure 11-4. The alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF flag bit and timer interrupts. The alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
AGREEMENT
INTERNAL DATA BUS LATCH ACRL ($001B) READ ACRL
READ ACRH RESET
READ ($FFFC)
ACRH ($001A)
TMR LSB /4 INTERNAL CLOCK (OSC / 2)
16-BIT COUNTER
NON-DISCLOSURE
Figure 11-4. Alternate Counter Block Diagram The alternate counter registers (ACRH and ACRL) shown in Figure 11-5 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter registers has no effect. Reset of the device presets the timer counter to $FFFC.
General Release Specification 160 Programmable Timer
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Programmable Timer
$001A Read: Write: Reset:
Bit 7 Bit 15
6 14
5 13
4 12
3 11
2 10
1 9
Bit 0 Bit 8
1
1
1
1
1
1
1
1
$001B Read: Write: Reset:
Bit 7 Bit 7
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
1
1
1
1
1
1
0
0
= Unimplemented
Figure 11-5. Alternate Counter Registers (ACRH and ACRL) The ACRL latch is a transparent read of the LSB until a read of the ACRH takes place. A read of the ACRH latches the LSB into the ACRL location until the ACRL is again read. The latched value remains fixed even if multiple reads of the ACRH take place before the next read of the ACRL. Therefore, when reading the MSB of the timer at ACRH, the LSB of the timer at ACRL must also be read to complete the read sequence. During power-on reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator startup delay. Because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit free-running counter or the TOF flag bit.
NOTE:
To prevent interrupts from occurring between readings of the ACRH and ACRL, set the I bit in the condition code register (CCR) before reading ACRH and clear the I bit after reading ACRL.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Programmable Timer
General Release Specification 161
NON-DISCLOSURE
AGREEMENT
REQUIRED
Programmable Timer REQUIRED 11.5 Input Capture Registers
The input capture function is a means to record the time at which an event occurs. The source of the event can be the change on an external pin (PB3/AN3/TCAP) or the CPF2 flag bit of voltage comparator 2 in the analog subsystem. The ICEN bit in the analog subsystem control register (ACR) at $001D selects which source is the input signal. When the input capture circuitry detects an active edge on the selected source, it latches the contents of the free-running timer counter registers into the input capture registers as shown in Figure 11-6.
AGREEMENT
NOTE:
Both the ICEN bit in the ACR and the IEDG bit in the TCR must be set when using voltage comparator 2 to trigger the input capture function. Latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. Latching the counter values at successive edges of opposite polarity measures the pulse width of the signal.
READ ICRH PB3 AN3 TCAP INPUT SELECT MUX CPF2 FLAG BIT FROM ANALOG SUBSYSTEM ICEN CONTROL BIT RESET $0012 EDGE SELECT & DETECT LOGIC ($FFFC) IEDG LATCH ICRH ($0014) ICRL ($0015)
INTERNAL DATA BUS
NON-DISCLOSURE
READ ICRL /4 INTERNAL CLOCK (OSC / 2) TIMER INTERRUPT REQUEST
16-BIT COUNTER INPUT CAPTURE (ICF)
IEDG
ICIE
TIMER CONTROL REG.
ICF TIMER STATUS REG. $0013 INTERNAL DATA BUS
Figure 11-6. Timer Input Capture Block Diagram
General Release Specification 162 Programmable Timer
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Programmable Timer
The input capture registers are made up of two 8-bit read-only registers (ICRH and ICRL) as shown in Figure 11-7. The input capture edge detector contains a Schmitt trigger to improve noise immunity. The edge that triggers the counter transfer is defined by the input edge bit (IEDG) in the TCR. Reset does not affect the contents of the input capture registers. The result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. This delay is required for internal synchronization. Resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles).
$0014 Read: Write: Reset: Unaffected by Reset Bit 7 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
$0015 Read: Write: Reset:
Bit 7 Bit 7
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
Unaffected by Reset = Unimplemented
Figure 11-7. Input Capture Registers (ICRH and ICRL) Reading the ICRH inhibits future captures until the ICRL is also read. Reading the ICRL after reading the timer status register (TSR) clears the ICF flag bit. There is no conflict between reading the ICRL and transfers from the free-running timer counters. The input capture registers always contain the free-running timer counter value which corresponds to the most recent input capture.
NOTE:
To prevent interrupts from occurring between readings of the ICRH and ICRL, set the I bit in the condition code register (CCR) before reading ICRH and clear the I bit after reading ICRL.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Programmable Timer
General Release Specification 163
NON-DISCLOSURE
AGREEMENT
REQUIRED
Programmable Timer REQUIRED 11.6 Output Compare Registers
The output compare function is a means of generating an output signal when the 16-bit timer counter reaches a selected value as shown in Figure 11-8. Software writes the selected value into the output compare registers. On every fourth internal clock cycle (every eight oscillator clock cycles), the output compare circuitry compares the value of the free-running timer counter to the value written in the output compare registers. When a match occurs, the timer transfers the output level (OLVL) from the timer control register (TCR) to the PB4/AN4/TCMP pin. Software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the PB4/AN4/TCMP pin.
AGREEMENT
R/W OCRH
OCRH ($0016)
OCRL ($0017) EDGE SELECT DETECT LOGIC /4
R/W OCRL PB4 AN4 TCMP INTERNAL CLOCK (OSC / 2) TIMER INTERRUPT REQUEST
16-BIT COMPARATOR
NON-DISCLOSURE
($FFFC) 16-BIT COUNTER OUTPUT COMPARE (OCF)
OLVL
OCIE
RESET
TIMER CONTROL REG. $0012
OCF
TIMER STATUS REG. $0013 INTERNAL DATA BUS
Figure 11-8. Timer Output Compare Block Diagram
General Release Specification 164 Programmable Timer
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
OLVL
Programmable Timer
The planned action on the PB4/AN4/TCMP pin depends on the value stored in the OLVL bit in the TCR, and it occurs when the value of the 16-bit free-running timer counter matches the value in the output compare registers shown in Figure 11-9. These registers are read/write bits and are unaffected by reset. Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written. Reading or writing to the OCRL after reading the TCR will clear the output compare flag bit (OCF). The output compare OLVL state will be clocked to its output latch regardless of the state of the OCF.
$0016 Read: Bit 15 Write: Reset: Unaffected by Reset 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0
$0017 Read:
Bit 7 Bit 7
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
Write: Reset: Unaffected by Reset
Figure 11-9. Output Compare Registers (OCRH and OCRL) To prevent OCF from being set between the time it is read and the time the output compare registers are updated, use this procedure: 1. Disable interrupts by setting the I bit in the condition code register. 2. Write to the OCRH. Compares are now inhibited until OCRL is written. 3. Read the TSR to arm the OCF for clearing. 4. Enable the output compare registers by writing to the OCRL. This also clears the OCF flag bit in the TSR. 5. Enable interrupts by clearing the I bit in the condition code register.
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General Release Specification 165
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REQUIRED
Programmable Timer REQUIRED
A software example of this procedure is shown in Table 11-1. Table 11-1. Output Compare Initialization Example
9B ... ... B7 B6 BF ... ... 9A SEI ... ... STA LDA STX ... ... CLI DISABLE INTERRUPTS ..... ..... INHIBIT OUTPUT COMPARE ARM OCF FLAG FOR CLEARING READY FOR NEXT COMPARE, OCF CLEARED ..... ..... ENABLE INTERRUPTS
16 13 17
OCRH TSR OCRL
AGREEMENT
11.7 Timer Control Register
The timer control register shown in Figure 11-10, performs these functions: * * * * * Enables input capture interrupts Enables output compare interrupts Enables timer overflow interrupts Controls the active edge polarity of the TCAP signal Controls the active level of the TCMP output
NON-DISCLOSURE
Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected.
$0012 Read: ICIE Write: Reset: 0 0 0 0 0 U = Unaffected 0 U 0 OCIE TOIE Bit 7 6 5 4 0 3 0 2 0 IEDG OLVL 1 Bit 0
= Unimplemented
Figure 11-10. Timer Control Register (TCR)
General Release Specification 166 Programmable Timer
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Programmable Timer
ICIE -- Input Capture Interrupt Enable This read/write bit enables interrupts caused by an active signal on the TCAP pin or from CPF2 flag bit of the analog subsystem voltage comparator 2. Reset clears the ICIE bit. 1 = Input capture interrupts enabled 0 = Input capture interrupts disabled OCIE -- Output Compare Interrupt Enable This read/write bit enables interrupts caused by an active match of the output compare function. Reset clears the OCIE bit. 1 = Output compare interrupts enabled 0 = Output compare interrupts disabled TOIE -- Timer Overflow Interrupt Enable This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit. 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled IEDG -- Input Capture Edge Select The state of this read/write bit determines whether a positive or negative transition triggers a transfer of the contents of the timer register to the input capture register. This transfer can occur due to transitions on the TCAP pin or the CPF2 flag bit of voltage comparator 2. Resets have no effect on the IEDG bit. 1 = Positive edge (low-to-high transition) triggers input capture 0 = Negative edge (high-to-low transition) triggers input capture
NOTE:
The IEDG bit must be set when either mode 2 or mode 3 of the analog subsystem is being used for A/D conversions. Otherwise, the input capture will not occur on the rising edge of the comparator 2 flag. OLVL -- Output Compare Output Level Select The state of this read/write bit determines whether a logic one or a logic zero is transferred to the TCMP pin when a successful output compare occurs. Resets clear the OLVL bit. 1 = Signal to TCMP pin goes high on output compare 0 = Signal to TCMP pin goes low on output compare
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Programmable Timer
General Release Specification 167
NON-DISCLOSURE
AGREEMENT
REQUIRED
Programmable Timer REQUIRED 11.8 Timer Status Register
The timer status register (TSR) shown in Figure 11-11 contains flags for these events: * An active signal on the TCAP pin or the CPF2 flag bit of voltage comparator 2 in the analog subsystem, transferring the contents of the timer registers to the input capture registers A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to the PB4/AN4/TCMP pin if that pin is set as an output An overflow of the timer registers from $FFFF to $0000
*
AGREEMENT
*
Writing to any of the bits in the TSR has no effect. Reset does not change the state of any of the flag bits in the TSR.
$0013 Read: Write: Reset: U U U 0 0 U = Unaffected 0 0 0 Bit 7 ICF 6 OCF 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0
= Unimplemented
NON-DISCLOSURE
Figure 11-11. Timer Status Register (TSR) ICF -- Input Capture Flag The ICF bit is set automatically when an edge of the selected polarity occurs on the TCAP pin. Clear the ICF bit by reading the timer status register with the ICF set and then reading the low byte (ICRL, $0015) of the input capture registers. Resets have no effect on ICF. OCF -- Output Compare Flag The OCF bit is set automatically when the value of the timer registers matches the contents of the output compare registers. Clear the OCF bit by reading the timer status register with the OCF set and then accessing the low byte (OCRL, $0017) of the output compare registers. Resets have no effect on OCF.
General Release Specification 168 Programmable Timer
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Programmable Timer
TOF -- Timer Overflow Flag The TOF bit is set automatically when the 16-bit timer counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with the TOF set and then accessing the low byte (TMRL, $0019) of the timer registers. Resets have no effect on TOF.
11.9 Timer Operation during Wait Mode
During wait mode, the 16-bit timer continues to operate normally and may generate an interrupt to trigger the MCU out of wait mode.
11.10 Timer Operation during Stop Mode
When the MCU enters stop mode, the free-running counter stops counting (the internal processor clock is stopped). It remains at that particular count value until stop mode is exited by applying a low signal to the IRQ pin, at which time the counter resumes from its stopped value as if nothing had happened. If stop mode is exited via an external reset (logic low applied to the RESET pin), the counter is forced to $FFFC. If a valid input capture edge occurs during stop mode, the input capture detect circuitry will be armed. This action does not set any flags or wake up the MCU, but when the MCU does wake up there will be an active input capture flag (and data) from the first valid edge. If the stop mode is exited by an external reset, no input capture flag or data will be present even if a valid input capture edge was detected during stop mode.
11.11 Timer Operation during Halt Mode
When the MCU enters halt mode, the functions and states of the 16-bit programmable timer are the same as for wait mode described above.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Programmable Timer
General Release Specification 169
NON-DISCLOSURE
AGREEMENT
REQUIRED
Programmable Timer REQUIRED NON-DISCLOSURE
General Release Specification 170 Programmable Timer
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 12. Instruction Set
12.1 Contents
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .176 12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .177 12.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .178 12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .180 12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 12.5 12.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Instruction Set
General Release Specification 171
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REQUIRED
Instruction Set REQUIRED 12.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.
AGREEMENT
12.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative
NON-DISCLOSURE
General Release Specification 172
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Instruction Set Freescale Semiconductor
Instruction Set
12.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
12.3.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
12.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
12.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Instruction Set
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Instruction Set REQUIRED
12.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.
AGREEMENT
12.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
NON-DISCLOSURE
12.3.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Freescale assembler determines the shortest form of indexed addressing.
General Release Specification 174 Instruction Set MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Instruction Set
12.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
12.4 Instruction Types
The MCU instructions fall into the following five categories: * * * * * Register/memory instructions Read-modify-write instructions Jump/branch instructions Bit manipulation instructions Control instructions
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Instruction Set
General Release Specification 175
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Instruction Set REQUIRED
12.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 12-1. Register/Memory Instructions
Instruction Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
AGREEMENT
Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator
NON-DISCLOSURE
General Release Specification 176
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Instruction Set Freescale Semiconductor
Instruction Set
12.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register.
NOTE:
Do not use read-modify-write operations on write-only registers. Table 12-2. Read-Modify-Write Instructions
Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
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Instruction Set REQUIRED
12.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register.
NON-DISCLOSURE
General Release Specification 178 Instruction Set
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MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Instruction Set
Table 12-3. Jump and Branch Instructions
Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL
BRCLR BRN BRSET BSR JMP JSR
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Instruction Set
General Release Specification 179
NON-DISCLOSURE
BRA
AGREEMENT
REQUIRED
Instruction Set REQUIRED
12.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 12-4. Bit Manipulation Instructions
Instruction Mnemonic BCLR BRCLR BRSET BSET
AGREEMENT
Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set
NON-DISCLOSURE
General Release Specification 180 Instruction Set
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Instruction Set
12.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 12-5. Control Instructions
Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA
WAIT
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REQUIRED
Instruction Set REQUIRED 12.5 Instruction Set Summary
Table 12-6. Instruction Set Summary
Address Mode Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
Operation
Description
H I NZC
Add with Carry
A (A) + (M) + (C)
--
AGREEMENT
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL
A9 ii 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 A4 ii 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3
Add without Carry
A (A) + (M)
--
Logical AND
A (A) (M)
----
--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
----
NON-DISCLOSURE
ff dd
Arithmetic Shift Right
b7 b0
C
----
ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- REL REL REL REL REL REL
BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C = 0
PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- ----------
General Release Specification 182 Instruction Set
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Cycles
Effect on CCR
Operand
Instruction Set
Table 12-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
H I NZC
---------- ----------
REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL
2F 2E
rr rr
Bit Test Accumulator with Memory Byte
(A) (M)
----
--
A5 ii 2 B5 dd 3 C5 hh ll 4 D5 ee ff 5 E5 ff 4 F5 3 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Cycles
3 3 6 2 2
Effect on CCR
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1
----------
PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel Branch if Bit n Clear
PC (PC) + 2 + rel ? Mn = 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- REL
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
BRSET n opr rel Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSET n opr
Set Bit n
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0
----------
REL
AD
rr
CLC CLI
Clear Carry Bit Clear Interrupt Mask
-------- 0 -- 0 ------
INH INH
98 9A
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Instruction Set
General Release Specification 183
NON-DISCLOSURE
AGREEMENT
REQUIRED
Operand
Instruction Set REQUIRED
Table 12-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X
Operation
Description
M $00 A $00 X $00 M $00 M $00
H I NZC
Clear Byte
---- 0 1 --
DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX
3F 4F 5F 6F 7F
dd
ff
AGREEMENT
Compare Accumulator with Memory Byte
(A) - (M)
----
A1 ii 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5
Complement Byte (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M)
----
1
ff
Compare Index Register with Memory Byte
(X) - (M)
----
A3 ii 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5
NON-DISCLOSURE
Decrement Byte
M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1
----
--
ff
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
----
--
A8 ii 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5
Increment Byte
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
----
--
ff
Unconditional Jump
PC Jump Address
----------
BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2
General Release Specification 184 Instruction Set
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Cycles
5 3 3 6 5
Effect on CCR
Operand
Instruction Set
Table 12-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X
Operation
Description
H I NZC
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address
Jump to Subroutine
----------
DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX
BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 A6 ii 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D dd dd 5 3 3 6 5 5 3 3 6 5 11 5 3 3 6 5 2
Load Index Register with Memory Byte
X (M)
----
--
Logical Shift Left (Same as ASL)
C b7 b0
0
----
ff dd
Logical Shift Right
0 b7 b0
C
---- 0
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
Negate Byte (Two's Complement)
----
ff
No Operation
----------
Logical OR Accumulator with Memory
A (A) (M)
----
--
AA ii 2 BA dd 3 CA hh ll 4 DA ee ff 5 EA ff 4 FA 3 39 49 59 69 79 dd 5 3 3 6 5
Rotate Byte Left through Carry Bit
C b7 b0
----
ff
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Instruction Set
General Release Specification 185
NON-DISCLOSURE
ff
AGREEMENT
Load Accumulator with Memory Byte
A (M)
----
--
Cycles
Effect on CCR
REQUIRED
Operand
Instruction Set REQUIRED
Table 12-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
H I NZC
Rotate Byte Right through Carry Bit
b7 b0
C
----
DIR INH INH IX1 IX INH
36 46 56 66 76 9C
dd
ff
Reset Stack Pointer
SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL)
----------
AGREEMENT
RTI
Return from Interrupt

INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X
Return from Subroutine
----------
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
81
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
----
A2 ii 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B 2 2
Set Carry Bit Set Interrupt Mask
C1 I1
-------- 1 -- 1 ------
NON-DISCLOSURE
Store Accumulator in Memory
M (A)
----
--
B7 dd 4 C7 hh ll 5 D7 ee ff 6 E7 ff 5 F7 4 8E 2
Stop Oscillator and Enable IRQ Pin
-- 0 ------
Store Index Register In Memory
M (X)
----
--
BF dd 4 CF hh ll 5 DF ee ff 6 EF ff 5 FF 4 A0 ii 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3
Subtract Memory Byte from Accumulator
A (A) - (M)
----
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ----------
INH
83
10
TAX
Transfer Accumulator to Index Register
INH
97
General Release Specification 186 Instruction Set
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Cycles
5 3 3 6 5 2 9 6 2
Effect on CCR
Operand
Instruction Set
Table 12-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
TST opr TSTA TSTX TST opr,X TST ,X TXA WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
Operation
Description
H I NZC
Test Memory Byte for Negative or Zero
(M) - $00
----
--
DIR INH INH IX1 IX INH INH
3D 4D 5D 6D 7D 9F 8F
dd
ff
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
A (X)
---------- -- 0 ------
Cycles
4 3 3 5 4 2 2
Effect on CCR
12.6 Opcode Map
See Table 12-7.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Instruction Set
General Release Specification 187
NON-DISCLOSURE
opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : --
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
AGREEMENT
REQUIRED
Operand
NON-DISCLOSURE
188
Instruction Set MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor General Release Specification
AGREEMENT
REQUIRED Instruction Set
Table 12-7. Opcode Map
Bit Manipulation DIR DIR
MSB LSB
Branch REL 2
DIR 3
Read-Modify-Write INH INH IX1 4 5 6
IX 7
Control INH INH 8
9 RTI INH 6 RTS INH
IMM A
2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2
DIR B
Register/Memory EXT IX2 C
4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3
IX1 E
4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1
IX F
3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX MSB LSB
0
1
9
D
5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2
0 1 2 3 4 5 6 7 8 9 A B C D E F
5 5 3 5 3 3 6 5 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BCLR0 BRN 3 DIR 2 DIR 2 REL 1 5 5 3 11 BRSET1 BSET1 BHI MUL 3 DIR 2 DIR 2 REL 1 INH 5 5 3 5 3 3 6 5 BRCLR1 BCLR1 BLS COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BCLR5 BMI 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BSET6 BMC INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BSET7 BIL 3 DIR 2 DIR 2 REL 1 5 5 3 5 3 3 6 5 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1
2 2 2
10 SWI INH
2 2 2 2 1 1 1 1 1 1 1 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2
2 STOP INH 2 2 WAIT TXA INH 1 INH
6 BSR REL 2 2 LDX 2 IMM 2 2 MSB LSB
3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3
0 1 2 3 4 5 6 7 8 9 A B C D E F
INH = Inherent IMM = Immediate DIR = Direct EXT = Extended
REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset
0
MSB of Opcode in Hexadecimal
LSB of Opcode in Hexadecimal
0
5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 13. Electrical Specifications
13.1 Contents
13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .191 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc). . . . . .192 Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc). . . . . .193 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . .194 DC Electrical Characteristics (3.0 Vdc). . . . . . . . . . . . . . . . . .195
13.10 Analog Subsystem Characteristics (5.0 Vdc) . . . . . . . . . . . . .198 13.11 Analog Subsystem Characteristics (3.0 Vdc) . . . . . . . . . . . . .199 13.12 Control Timing (5.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 13.13 Control Timing (3.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 13.14 SIOP Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . .202 13.15 SIOP Timing (VDD = 3.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . .203 13.16 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Electrical Specifications
General Release Specification 189
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specifications REQUIRED 13.2 Introduction
This section contains the electrical and timing specifications.
13.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. Keep VIN and VOUT within the range VSS (VIN or VOUT) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating Supply Voltage Self-Check Mode (IRQ Pin Only) Current Drain Per Pin Excluding VDD and VSS Symbol VDD VIN I TJ Tstg Value -0.3 to +7.0 VSS -0.3 to + 12 25 +150 -65 to +150 Unit V V mA C C
NON-DISCLOSURE
AGREEMENT
Operating Junction Temperature Storage Temperature Range
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to 13.8 DC Electrical Characteristics (5.0 Vdc) and 13.9 DC Electrical Characteristics (3.0 Vdc) for guaranteed operating conditions.
General Release Specification 190 Electrical Specifications
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Electrical Specifications
13.4 Operating Temperature Range
Characteristic Operating Temperature Range Extended Symbol TA Value TL to TH -40 to +85 Unit C
13.5 Thermal Characteristics
Characteristic Thermal Resistance Plastic SOIC Symbol JA Value 60 Unit C/W
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Electrical Specifications
General Release Specification 191
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specifications REQUIRED 13.6 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc)
Characteristic RUN (Analog and LVR Disabled) Internal Low-Power Oscillator at 100 kHz Internal Low-Power Oscillator at 500 kHz External Oscillator Running at 4.2 MHz WAIT (Analog and LVR Disabled) Internal Low-Power Oscillator at 100 kHz Internal Low-Power Oscillator at 500 kHz External Oscillator Running at 4.2 MHz STOP (Analog and LVR Disabled) 25 C -40 C to 85 C Incremental IDD for Enabled Modules LVR Analog Subsystem Symbol Min -- -- -- -- -- -- -- -- -- -- Typ 150 375 3.00 45 75 1.00 2 4 5 380 Max 568 1100 5.20 85 375 2.20 10 20 15 475 Unit A A mA A A mA A A A A
IDD
IDD
AGREEMENT
IDD
IDD
NON-DISCLOSURE
NOTES: 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL TA TH, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 C only 4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD -0.2 Vdc, OSC1 = VDD.
General Release Specification 192 Electrical Specifications
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Electrical Specifications
13.7 Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc)
Characteristic RUN (Analog and LVR Disabled) Internal Low-Power Oscillator at 100 kHz Internal Low-Power Oscillator at 500 kHz External Oscillator Running at 2.1 MHz WAIT (Analog and LVR Disabled) Internal Low-Power Oscillator at 100 kHz Internal Low-Power Oscillator at 500 kHz External Oscillator Running at 2.1 MHz STOP (Analog and LVR Disabled) 25 C -40 C to 85 C Incremental IDD for Enabled Modules LVR Analog Subsystem Symbol Min -- -- -- -- -- -- -- -- -- -- Typ 70 320 1.25 20 40 0.50 1 2 5 380 Max 320 800 2.60 65 250 1.10 5 10 15 475 Unit A A mA A A mA A A A A
IDD
IDD
IDD
IDD
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Electrical Specifications
General Release Specification 193
NON-DISCLOSURE
NOTES: 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL TA TH, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 C only 4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD -0.2 Vdc, OSC1 = VDD.
AGREEMENT
REQUIRED
Electrical Specifications REQUIRED 13.8 DC Electrical Characteristics (5.0 Vdc)
Characteristic Output Voltage Iload = 10.0 A Iload = -10.0 A Output High Voltage (Iload = -0.8 mA) PB0:PB7 (Iload = -4.0 mA) PA0:PA5, PB4, PC0:PC7 Output Low Voltage (Iload = 1.6 mA) PB0:PB7, RESET (Iload = 10 mA) PA0:PA5, PB4, PC0:PC7 (Iload = 15 mA) PA0:PA5, PB4, PC0:PC7 High Source Current Total for All (6) PA0:PA5 Pins and PB4 Total for All (8) PC0:PC7 Pins High Sink Current Total for All (6) PA0:PA5 Pins and PB4 Total for All (8) PC0:PC7 Pins Input High Voltage PA0:PA5, PB0:PB7, PC0:PC7, RESET, OSC1, IRQ/VPP Input Low Voltage PA0:PA5, PB0:PB7, PC0:PC7, RESET, OSC1, IRQ/VPP Input Current OSC1, IRQ/VPP Input Current RESET (Pullup, Source) RESET (Pulldown, Sink) I/O Ports High-Z Leakage Current (Pulldowns Off) PA0:PA6, PB0:PB7, PC0:PC7 Input Pulldown Current PA0:PA5, PB0:PB7, PC0:PC7 (VIN = VIH = 0.7 x VDD) PA0:PA5, PB0:PB7, PC0:PC7 (VIN = VIL = 0.3 x VDD) Symbol VOL VOH Min -- VDD -0.1 VDD -0.8 VDD -0.8 -- -- -- -- -- -- -- 0.7 x VDD Typ -- -- -- -- -- -- -- -- -- -- -- Max 0.1 -- -- -- 0.4 0.4 1.5 20 30 40 60 VDD Unit V
VOH
V
AGREEMENT
VOL
V
IOH
mA
IOL
mA
VIH
--
V
NON-DISCLOSURE
VIL
VSS
--
0.3 x VDD
V
IIN
-1
--
1
A A mA A A
IIN
10 -6 -2
-- -- --
-- -- 2
IOZ
IIL
40 25
100 65
280 190
NOTES: 1. +4.5 VDD +5.5 V, VSS = 0 V, TL TA TH, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 C only 4. PC0:PC7 parameters only apply to MC68HC05JP6
General Release Specification 194 Electrical Specifications
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Electrical Specifications
13.9 DC Electrical Characteristics (3.0 Vdc)
Characteristic Output Voltage Iload = 10.0 A Iload = -10.0 A Output High Voltage (Iload = -0.2 mA) PB0:PB7, RESET (Iload = -2.0 mA) PA0:PA5, PB4, PC0:PC7 Output Low Voltage (Iload = 1.6 mA) PB0:PB7, RESET (Iload = 5.0 mA) PA0:PA5, PB4, PC0:PC7 High Source Current Total for All (6) PA0:PA5 Pins and PB4 Total for All (8) PC0:PC7 Pins High Sink Current Total for All (6) PA0:PA5 Pins and PB4 Total for All (8) PC0:PC7 Pins Input High Voltage PA0:PA5, PB0:PB7, PC0:PC7, RESET, OSC1, IRQ/VPP Input Low Voltage PA0:PA5, PB0:PB7, PC0:PC7, RESET, OSC1, IRQ/VPP Input Current OSC1, IRQ/VPP Input Current RESET (Pullup, Source) RESET (Pulldown, Sink) I/O Ports High-Z Leakage Current (Pulldowns Off) PA0:PA6, PB0:PB7, PC0:PC7 Input Pulldown Current PA0:PA5, PB0:PB7, PC0:PC7 (VDD = VIH = 0.7 x VDD) PA0:PA5, PB0:PB7, PC0:PC7 (VIN = VIL = 0.3 x VDD) Symbol VOL VOH VOH Min -- VDD -0.1 VDD -0.8 Typ -- -- -- Max 0.1 -- -- Unit V
V
IOH
-- -- -- -- 0.7 x VDD
-- -- -- -- --
20 30 40 60 VDD
mA
IOL
mA
VIH
V
VIL
VSS
--
0.2 x VDD
V
IIN
-1
--
1
A A mA A A
IIN
5 -3 -2
-- -- --
-- -- 2
IOZ
IIL
10 4
25 20
75 40
NOTES: 1. +2.7 VDD +3.3 V, VSS = 0 V, TL TA TH, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 C only 4. PC0:PC7 parameters only apply to MC68HC05JP6
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Electrical Specifications
General Release Specification 195
NON-DISCLOSURE
AGREEMENT
VOL
-- --
-- --
0.3 0.3
V
REQUIRED
Electrical Specifications REQUIRED
2.50 MAXIMUM MINIMUM INTERNAL BUS FREQUENCY (MHz) 2.00
1.50
1.00
AGREEMENT
0.50
0 12 K
24 K RC OSCILLATOR RESISTANCE
4 7K
Figure 13-1. Overall Internal Operating Frequency Range versus Resistance for VDD = 5 V 10%, -40 C to 85 C
2.50 VDD = 5.5 V VDD = 4.5 V INTERNAL BUS FREQUENCY (MHz) 2.00
NON-DISCLOSURE
1.50
1.00
0.50
0 12 K
24 K RC OSCILLATOR RESISTANCE
47 K
Figure 13-2. Typical Internal Operating Frequency Range versus Resistance for High VDD Operating Range, 25 C
General Release Specification 196 Electrical Specifications
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Electrical Specifications
2.20 2.00 INTERNAL BUS FREQUENCY (MHz) 1.80 1.60 1.40 1.20 1.00 0.80 0.60 MAXIMUM MINIMUM
0.20 0 12 K 24 K RC OSCILLATOR RESISTANCE 47 K
Figure 13-3. Overall Internal Operating Frequency Range versus Resistance for VDD = 3 V 10%, -40 C to 85 C
2.20 2.00 INTERNAL BUS FREQUENCY (MHz) 1.80 1.60 VDD = 3.3 V VDD = 2.7 V
1.20 1.00 0.80 0.60 0.40 0.20 0 12 K 24 K RC OSCILLATOR RESISTANCE 47 K
Figure 13-4. Typical Internal Operating Frequency Range versus Resistance for Low VDD Operating Range, 25 C
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Electrical Specifications
General Release Specification 197
NON-DISCLOSURE
1.40
AGREEMENT
0.40
REQUIRED
Electrical Specifications REQUIRED 13.10 Analog Subsystem Characteristics (5.0 Vdc)
Characteristic Voltage Comparators Input Offset Voltage Common-Mode Range Comparator 1 Input Impedance Comparator 2 Input Impedance Direct Input to Comparator 2 (HOLD = 1, DHOLD = 0) Divider Input to Comparator 2 (HOLD = 0, DHOLD = 1) Input Divider Ratio (Comparator 2, HOLD = 0, DHOLD =1) VIN = 0 to VDD -1.5 V Analog Subsystem Internal VSS Offset Sum of Comparator Offset and IR Drop through VSS Channel Selection Multiplexer Switch Resistance External Current Source (PB0/AN0) Source Current (VOUT = VDD/2) Source Current Linearity (VOUT = 0 to VDD -1.5 Vdc) Discharge Sink Current (VOUT = 0.4 V) External Capacitor (Connected to PB0/AN0) Voltage Range Discharge Time Value of External Ramping Capacitor Internal Sample and Hold Capacitor Capacitance Charge/Discharge Time (0 to 3.5 Vdc) Direct Connection (HOLD = 1, DHOLD = 0) Divided Connection (HOLD = 0, DHOLD = 1) Temperature Diode Connection (HOLD = 1, DHOLD = 1) Leakage Discharge Rate Internal Temperature Sensing Diode Voltage (at TJ = 25 C) Temperature Change in Voltage
NOTE: 1. +4.5 VDD +5.5 V, VSS = 0 V, TL TA TH, unless otherwise noted
Symbol VIO VCMR ZIN ZIN ZIN RDIV VAOFF RMUX ICHG ICHG IDIS VCAP tDIS CEXT CSH tSHCHG tSHDCHG tSHTCHG CSHDIS VD TCD
Min -- -- 800 800 80 0.49 20 -- 85 -- 1.1 VSS 5 -- 8 1 2 1 -- 0.65 2.0
Max 15 VDD -1.5 -- -- -- 0.51 40 3 113 1 -- VDD -1.5 10 2 13 -- -- -- 0.2 0.71 2.2
Unit mV V k k k -- mV k A %FS mA V ms/F F pF s s s V/sec V mV/C
NON-DISCLOSURE
AGREEMENT
General Release Specification 198 Electrical Specifications
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Electrical Specifications
13.11 Analog Subsystem Characteristics (3.0 Vdc)
Characteristic Voltage Comparators Input Offset Voltage Common-Mode Range Comparator 1 Input Impedance Comparator 2 Input Impedance Direct Input to Comparator 2 (HOLD = 1, DHOLD = 0) Divider Input to Comparator 2 (HOLD = 0, DHOLD = 1) Input Divider Ratio (Comparator 2, HOLD = 0, DHOLD =1) VIN = 0 to VDD -1.5 V Analog Subsystem Internal VSS Offset Multiplexer Switch Resistance External Current Source (PB0/AN0) Source Current (VOUT = VDD/2) Source Current Linearity (VOUT = 0 to VDD -1.5 Vdc) Discharge Sink Current (VOUT = 0.4 V) External Capacitor (Connected to PB0/AN0) Voltage Range Discharge Time Value of External Ramping Capacitor Internal Sample and Hold Capacitor Capacitance Charge/Discharge Time (0 to 3.5 Vdc) Direct Connection (HOLD = 1, DHOLD = 0) Divided Connection (HOLD = 0, DHOLD = 1) Temperature Diode Connection (HOLD = 1, DHOLD = 1) Leakage Discharge Rate Internal Temperature Sensing Diode Voltage (at TJ = 25 C) Temperature Change in Voltage
NOTE: 1. +2.7 VDD +3.3 V, VSS = 0 V, TL TA TH, unless otherwise noted
Symbol VIO VCMR ZIN ZIN ZIN RDIV VAOFF RMUX ICHG ICHG IDIS VCAP tDIS CEXT CSH tSHCHG tSHDCHG tSHTCHG CSHDIS VD TCD
Min -- -- 800 800 80 0.49 10 -- 75 -- 1 VSS 5 -- 8 1 2 1 -- 0.65 2.0
Max 15 VDD -1.5 -- -- -- 0.51 30 5 104 1 -- VDD -1.5 10 2 13 -- -- -- 0.1 0.71 2.2
Unit mV V k k k -- mV k A %FS mA V ms/F F pF s s s V/sec V mV/C
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Electrical Specifications
General Release Specification 199
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specifications REQUIRED 13.12 Control Timing (5.0 Vdc)
Characteristic Frequency of Oscillation (OSC) RC Oscillator Option Crystal Oscillator Option External Clock Source Internal Low-Power Oscillator Standard Product (100 kHz Nominal) Mask Option (500 kHz Nominal) Internal Operating Frequency, Crystal, or External Clock (fOSC/2) RC Oscillator Option Crystal Oscillator Option External Clock Source Internal Low-Power Oscillator Standard Product (100 kHz Nominal) Mask Option (500 kHz Nominal) Cycle Time (1/fOP) External Oscillator or Clock Source Internal Low-Power Oscillator Standard Product (100 kHz Nominal) Mask Option (500 kHz Nominal) 16-Bit Timer Resolution Input Capture (TCAP) Pulse Width Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width (External Clock Input) Analog Subsystem Response Voltage Comparators Switching Time (10-mV Overdrive, Either Input) Comparator Power-Up Delay (Bias Circuit Already Powered Up) External Current Source (PB0/AN0) Switching Time (IDIS to IRAMP) Power-Up Delay (Bias Circuit Already Powered Up) Bias Circuit Power-Up Delay Symbol Min -- 0.1 DC 60 300 -- 0.05 DC 30 150 476 tCYC 14.29 2.86 tRESL tTH, tTL tILIH tILIL tOH, tOL 4.0 284 284 see Note 2 110 33.33 6.67 -- -- -- -- -- Max 4.2 4.2 4.2 140 700 2.1 2.1 2.1 70 350 -- Unit MHz MHz MHz kHz kHz MHz MHz MHz kHz kHz ns s s tCYC ns ns tCYC ns
fOSC
AGREEMENT
fOP
NON-DISCLOSURE
tCPROP tCDELAY tISTART tIDELAY tBDELAY
-- -- -- -- --
2 2 1 2 2
s s s s s
NOTES: 1. +4.5 VDD +5.5 V, VSS = 0 V, TL TA TH, unless otherwise noted 2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC.
General Release Specification 200 Electrical Specifications
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Electrical Specifications
13.13 Control Timing (3.0 Vdc)
Characteristic Frequency of Oscillation (OSC) RC Oscillator Option Crystal Oscillator Option External Clock Source Internal Low-Power Oscillator Standard Product (100 kHz Nominal) Mask Option (500 kHz Nominal) Internal Operating Frequency, Crystal, or External Clock (fOSC/2) RC Oscillator Option Crystal Oscillator Option External Clock Source Internal Low-Power Oscillator Standard Product (100 kHz Nominal) Mask Option (500 kHz Nominal) Cycle Time (1/fOP) External Oscillator or Clock Source Internal Low-Power Oscillator Standard Product (100 kHz Nominal) Mask Option (500 kHz Nominal) 16-Bit Timer Resolution Input Capture (TCAP) Pulse Width Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width (External Clock Input) Analog Subsystem Response Voltage Comparators Switching Time (10-mV Overdrive, Either Input) Comparator Power-Up Delay (Bias Circuit Already Powered Up) External Current Source (PB0/AN0) Switching Time (IDIS to IRAMP) Power-Up Delay (Bias Circuit Already Powered Up) Bias Circuit Power-Up Delay Symbol Min -- 0.1 DC 60 300 -- 0.05 DC 30 150 952 tCYC 14.29 2.86 tRESL tTH, tTL tILIH tILIL tOH, tOL 4.0 284 284 see Note 2 110 33.33 6.67 -- -- -- -- -- Max 2.1 2.1 2.1 140 700 1.05 1.05 1.05 70 350 -- Unit MHz MHz MHz kHz kHz MHz MHz MHz kHz kHz ns s s tCYC ns ns tCYC ns
fOSC
fOP
tCPROP tCDELAY tISTART tIDELAY tBDELAY
-- -- -- -- --
2 2 1 2 2
s s s s s
NOTES: 1. +2.7 VDD +3.3 V, VSS = 0 V, TL TA TH, unless otherwise noted 2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Electrical Specifications
General Release Specification 201
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specifications REQUIRED 13.14 SIOP Timing (VDD = 5.0 Vdc)
Characteristic Frequency of Operation Master Slave Cycle Time Master Slave Clock (SCK) Low Time (fOP = 4.2 MHz) SDO Data Valid Time SDO Hold Time SDI Setup Time SDI Hold Time Symbol fSIOP(M) fSIOP(S) tSCK(M) tSCK(M) tSCKL tV tHO tS tH Min 0.25 x fOP DC 4.0 x tCYC -- 466 -- 0 100 100 Typ 0.25 x fOP -- 4.0 x tCYC -- -- -- -- -- -- Max 0.25 x fOP 1050 4.0 x tCYC 3.8 -- 200 -- -- -- Unit kHz
s ns ns ns ns ns
AGREEMENT
NOTE: 1. +4.5 VDD +5.5 V, VSS = 0 V, TL TA TH, unless otherwise noted
tSCK tSCKL
NON-DISCLOSURE
SCK tV tHO
SDO
MSB tS
BIT 1
LSB
SDI
MSB
VALID DATA tH
LSB
Figure 13-5. SIOP Timing Diagram
General Release Specification 202 Electrical Specifications
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Electrical Specifications
13.15 SIOP Timing (VDD = 3.0 Vdc)
Characteristic Frequency of Operation Master Slave Cycle Time Master Slave Clock (SCK) Low Time (fOP = 4.2 MHz) SDO Data Valid Time SDO Hold Time SDI Setup Time SDI Hold Time Symbol fSIOP(M) fSIOP(S) tSCK(M) tSCK(M) tSCKL tV tHO tS tH Min 0.25 x fOP DC 4.0 x tCYC -- 932 -- 0 200 200 Typ 0.25 x fOP -- 4.0 x tCYC -- -- -- -- -- -- Max 0.25 x fOP 525 4.0 x tCYC 1.9 -- 400 -- -- -- Unit
kHz
s ns ns ns ns ns
NOTE: 1. +2.7 VDD +3.3 V, VSS = 0 V, TL TA TH, unless otherwise noted
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Electrical Specifications
General Release Specification 203
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specifications REQUIRED 13.16 Reset Characteristics
Characteristic Low-Voltage Reset Rising Recovery Voltage Falling Reset Voltage LVR Hysteresis POR Recovery Voltage (see Note 2) POR VDD Slew Rate (see Note 2) Rising (see Note 2) Falling (see Note 2) RESET Pulse Width (when Bus Clock Active) RESET Pulldown Pulse Width (from Internal Reset) Symbol VLVRR VLVRF VLVRH VPOR SVDDR SVDDF tRL tRPD Min 2.4 2.3 100 0 -- -- 1.5 3 Typ 3.4 3.3 -- -- -- -- -- -- Max 4.4 4.3 -- 100 0.1 0.05 -- 4 Unit V V mV mV V/s tCYC tCYC
AGREEMENT
NOTE: 1. +2.7 VDD +5.5 V, VSS = 0 V, TL TA TH, unless otherwise noted 2. By design, not tested
OSC11
tRL RESET 4064 or 16 tcyc2 INTERNAL CLOCK3 INTERNAL ADDRESS BUS3 INTERNAL DATA BUS3
NON-DISCLOSURE
1FFE
1FFF
NEW PCH
NEW PCL
NEW PCH
NEW PCL
Op code
NOTES: 1. Represents the internal gating of the OSC1 pin 2. Normal delay of 4064 tCYC or short delay option of 16 tCYC 3. Internal timing signal and data information not available externally
Figure 13-6. Stop Recovery Timing Diagram
General Release Specification 204 Electrical Specifications
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Electrical Specifications
INTERNAL RESET1
RESET PIN tRPD INTERNAL CLOCK3 INTERNAL ADDRESS BUS3 INTERNAL DATA BUS3
4064 or 16 tcyc2
1FFE
1FFF
NEW PCH
NEW PCL
NEW PCH
NEW PCL
NOTES: 1. Represents the internal reset from low-voltage reset, illegal opcode fetch, or COP watchdog timeout 2. Only if reset occurs during normal delay of 4064 tCYC or short delay option of 16 tCYC for initial power-up or stop recovery 3. Internal timing signal and data information not available externally
Figure 13-7. Internal Reset Timing Diagram
VDD VLVRH
VLVRL
LOW VOLTAGE RESET
RESET PIN1 INTERNAL CLOCK3 INTERNAL ADDRESS BUS3 INTERNAL DATA BUS3
tRPD
4064 or 16 tcyc2
1FFE
1FFF
NEW PCH
NEW PCL
NEW PCH
NEW PCL
NOTES: 1. RESET pin pulled down by internal device 2 Only if LVR occurs during normal delay of 4064 tCYC or short delay option of 16 tCYC for initial power-up or stop recovery 3 Internal timing signal and data information not available externally
Figure 13-8. Low-Voltage Reset Timing Diagram
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Electrical Specifications General Release Specification 205
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specifications REQUIRED NON-DISCLOSURE
General Release Specification 206 Electrical Specifications
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 14. Mechanical Specifications
14.1 Contents
14.2 14.3 14.4 14.5 14.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 20-Pin Plastic Dual In-Line Package (Case 738) . . . . . . . . . .208 20-Pin Small Outline Integrated Circuit (Case 751D) . . . . . . .208 28-Pin Plastic Dual In-Line Package (Case 710) . . . . . . . . . .209 28-Pin Small Outline Integrated Circuit (Case 751F) . . . . . . .209
14.2 Introduction
The MC68HC05JJ6 is available in both a 20-pin plastic dual in-line package (PDIP) and a small outline integrated circuit (SOIC) package. The MC68HC05JP6 is available in a 28-pin plastic dual in-line package (PDIP) and a 28-pin small outline integrated circuit (SOIC) package. The following figure shows the latest package at the time of this publication. To make sure that you have the latest package specifications, please visit the Freescale website at http://freescale.com. Follow wwweb on-line instructions to retrieve the current mechanical specifications.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Mechanical Specifications
General Release Specification 207
NON-DISCLOSURE
AGREEMENT
REQUIRED
Mechanical Specifications REQUIRED 14.3 20-Pin Plastic Dual In-Line Package (Case 738)
-A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0 15 0.51 1.01
B
1 10
C
L
AGREEMENT
-TSEATING PLANE
K M E G F D 20 PL 0.25 (0.010)
M
N J 20 PL 0.25 (0.010) TA
M
M
TB
M
14.4 20-Pin Small Outline Integrated Circuit (Case 751D)
-A-
NON-DISCLOSURE
20
11
-B-
P 10 PL 0.010 (0.25)
M
B
M
1
10
D
20 PL
0.010 (0.25)
M
TA
S
B
S
J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029
F R X 45 C -TG
18 PL SEATING PLANE
K
M
General Release Specification 208 Mechanical Specifications
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Mechanical Specifications
14.5 28-Pin Plastic Dual In-Line Package (Case 710)
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
28
15
B
1 14
A N
C
L
H
G F D
K
SEATING PLANE
M
J
14.6 28-Pin Small Outline Integrated Circuit (Case 751F)
-A28 15 14X
-B1 14
M
B
M
28X D
0.010 (0.25)
M
T
A
S
B
S
M R X 45
-T26X
C G K -TSEATING PLANE
F J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 17.80 18.05 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8 0 10.05 10.55 0.75 0.25
INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 8 0 0.395 0.415 0.010 0.029
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Mechanical Specifications
General Release Specification 209
NON-DISCLOSURE
P 0.010 (0.25)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.
AGREEMENT
REQUIRED
Mechanical Specifications REQUIRED NON-DISCLOSURE
General Release Specification 210 Mechanical Specifications
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
General Release Specification -- MC68HC05JJ6/MC68HC05JP6
Section 15. Ordering Information
15.1 Contents
15.2 15.3 15.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 MC68HC05JJ6 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .212 MC68HC05JP6 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .212
15.2 Introduction
This section contains instructions for ordering custom-masked ROM MCUs.
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Ordering Information
General Release Specification 211
NON-DISCLOSURE
AGREEMENT
REQUIRED
Ordering Information REQUIRED 15.3 MC68HC05JJ6 Order Numbers
This table shows the MC order numbers for the available 20-pin package types.
Package Type Plastic DIP(2) Plastic DIP SOIC(4) SOIC Plastic DIP Plastic DIP SOIC SOIC EPO Oscill. Type(1) Xtal Xtal Xtal Xtal RC RC RC RC LPO Freq. (kHz) 100 or 500 100 or 500 100 or 500 100 or 500 100 or 500 100 or 500 100 or 500 100 or 500 Operating Temperature Range -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C
Order Number
MC68HC05JJ6CP MC68HC05JJ6CPE(3) MC68HC05JJ6CDW MC68HC05JJ6CDWE MC68HC05JJ6CP MC68HC05JJ6CPE MC68HC05JJ6CDW MC68HC05JJ6CDWE
NON-DISCLOSURE
AGREEMENT
1. Crystal/Ceramic Resonator or RC Oscillator 2. Plastic Dual In-Line Package (P, Case Outline 738) 3. E indicates Pb Free and meets RoHS requirements. 4. Small Outline Integrated Circuit Package (DW, Case Outline 751D)
15.4 MC68HC05JP6 Order Numbers
This table shows the MC order numbers for the available 28-pin package types.
Package Type Plastic DIP(2) Plastic DIP(3) EPO Oscill. Type(1) Xtal Xtal LPO Freq. (kHz) 100 or 500 100 or 500 Operating Temperature Range -40 C to 85 C -40 C to 85 C
Order Number
MC68HC05JP6CP MC68HC05JP6CPE(4)
General Release Specification 212 Ordering Information
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
Ordering Information
Package Type SOIC(5) SOIC(6) Plastic DIP Plastic DIP SOIC SOIC
EPO Oscill. Type(1) Xtal Xtal RC RC RC RC
LPO Freq. (kHz) 100 or 500 100 or 500 100 or 500 100 or 500 100 or 500 100 or 500
Operating Temperature Range -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C
Order Number
MC68HC05JP6CDW MC68HC05JP6CDWE MC68HC05JP6CP MC68HC05JP6CPE MC68HC05JP6CDW MC68HC05JP6CDWE
1. Crystal/Ceramic Resonator or RC Oscillator 2. Plastic Dual In-Line Package (P, Case Outline 710) 3. Plastic Dual In-Line Package (P, Case Outline 710) 4. E indicates Pb Free and meets RoHS requirements. 5. Small Outline Integrated Circuit Package (DW, Case Outline 751F) 6. Small Outline Integrated Circuit Package (DW, Case Outline 751F)
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor Ordering Information
General Release Specification 213
NON-DISCLOSURE
AGREEMENT
REQUIRED
Ordering Information REQUIRED NON-DISCLOSURE
General Release Specification 214 Ordering Information
AGREEMENT
MC68HC05JJ6/MC68HC05JP6 -- Rev. 3.2 Freescale Semiconductor
How to Reach Us:
Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Rev. 3.2 HC05JJ6GRS/D 01/2007
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Price & Availability of MC68HC05JP6CPE

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